1# Atmel SAM MCU series general configuration options
2
3# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
7
8menu "Clocks"
9
10config SOC_ATMEL_SAM_EXT_SLCK
11	bool "Use external crystal oscillator for slow clock"
12	help
13	  Says y if you want to use external 32 kHz crystal oscillator to drive
14	  the slow clock. Note that this adds a few seconds to boot time, as the
15	  crystal needs to stabilize after power-up.
16
17	  Says n if you do not need accurate and precise timers. The slow clock
18	  will be driven by the internal fast RC oscillator running at 32 kHz.
19
20config SOC_ATMEL_SAM_EXT_MAINCK
21	bool "Use external crystal oscillator for main clock"
22	default y
23	help
24	  The main clock is being used to drive the PLL, and thus driving the
25	  processor clock.
26
27	  Says y if you want to use external crystal oscillator to drive the
28	  main clock. Note that this adds about a second to boot time, as the
29	  crystal needs to stabilize after power-up.
30
31	  The crystal used here can be from 3 to 20 MHz.
32
33	  Says n here will use the internal fast RC oscillator running at 12 MHz.
34
35menu "PLL A"
36
37config SOC_ATMEL_SAM_PLLA_MULA
38	int "PLL MULA"
39	default  6 if SOC_SERIES_SAM3X
40	default  9 if SOC_SERIES_SAM4S  || SOC_SERIES_SAM4E
41	default 24 if SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
42	range 1 62
43	help
44	  This is the multiplier (MULA) used by the PLL.
45	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
46
47	  Board config file can override this settings for a particular board.
48
49	  With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
50	  the main clock frequency.
51
52config SOC_ATMEL_SAM_PLLA_DIVA
53	int "PLL DIVA"
54	default 1
55	range 1 $(UINT8_MAX)
56	help
57	  This is the divider (DIVA) used by the PLL.
58	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
59
60	  Board config file can override this settings
61	  for a particular board.
62
63	  With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
64	  the main clock frequency.
65
66config SOC_ATMEL_SAM_MDIV
67	int "MDIV"
68	depends on SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
69	default 2
70	range 1 4
71	help
72	  This divisor defines a ratio between processor clock (HCLK)
73	  and master clock (MCK) where the maximum value is 150MHz:
74	  MCK = HCLK / MDIV
75
76endmenu # PLL A
77endmenu # clocks
78
79config SOC_ATMEL_SAM_WAIT_MODE
80	bool "CPU goes to Wait mode instead of Sleep mode"
81	depends on SOC_ATMEL_SAM_EXT_MAINCK
82	default y if DEBUG
83	help
84	  For JTAG debugging CPU clock (HCLK) should not stop. In order to
85	  achieve this, make CPU go to Wait mode instead of Sleep mode while
86	  using external crystal oscillator for main clock.
87
88config SOC_ATMEL_SAM_DISABLE_ERASE_PIN
89	bool "Disable ERASE pin"
90	help
91	  At reset ERASE pin is configured in System IO mode. Asserting the
92	  ERASE pin at '1' will completely erase Flash memory. Setting this
93	  option will switch the pin to general IO mode giving control of the
94	  pin to the GPIO module.
95
96endif # SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
97