1/*
2 * Copyright (c) 2022 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8};
9
10&pinctrl {
11	shd_cs0_n_gpio055_sleep: shd_cs0_n_gpio055_sleep {
12		pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF2) >;
13		low-power-enable;
14	};
15	shd_clk_gpio056_sleep: shd_clk_gpio056_sleep {
16		pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF2) >;
17		low-power-enable;
18	};
19	shd_io0_gpio223_sleep: shd_io0_gpio223_sleep {
20		pinmux = < MCHP_XEC_PINMUX(0223, MCHP_AF1) >;
21		low-power-enable;
22	};
23	shd_io1_gpio224_sleep: shd_io1_gpio224_sleep {
24		pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF2) >;
25		low-power-enable;
26	};
27	shd_io2_gpio227_sleep: shd_io2_gpio227_sleep {
28		pinmux = < MCHP_XEC_PINMUX(0227, MCHP_AF1) >;
29		low-power-enable;
30	};
31	shd_io3_gpio016_sleep: shd_io3_gpio016_sleep {
32		pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF2) >;
33		low-power-enable;
34	};
35
36	gpio_off_gpio116: gpio_gpio116 {
37		pinmux = < MCHP_XEC_PINMUX(0116, MCHP_GPIO) >;
38		low-power-enable;
39	};
40	gpio_off_gpio117: gpio_gpio117 {
41		pinmux = < MCHP_XEC_PINMUX(0117, MCHP_GPIO) >;
42		low-power-enable;
43	};
44	gpio_off_gpio074: gpio_gpio074 {
45		pinmux = < MCHP_XEC_PINMUX(074, MCHP_GPIO) >;
46		low-power-enable;
47	};
48	gpio_off_gpio075: gpio_gpio075 {
49		pinmux = < MCHP_XEC_PINMUX(075, MCHP_GPIO) >;
50		low-power-enable;
51	};
52	gpio_off_gpio076: gpio_gpio076 {
53		pinmux = < MCHP_XEC_PINMUX(076, MCHP_GPIO) >;
54		low-power-enable;
55	};
56};
57
58/* Controller drives chip select
59 * For MEC1727 we need to disable internal SPI pins before
60 * enabling shared SPI pins. This can be done by adding
61 * the gpio_off_* for internal pins at the beginning of
62 * pinctrl-0 <>
63 */
64&spi0 {
65	compatible = "microchip,xec-qmspi-ldma";
66	status = "okay";
67
68	pinctrl-0 = < &shd_cs0_n_gpio055
69		      &shd_clk_gpio056
70		      &shd_io0_gpio223
71		      &shd_io1_gpio224
72		      &shd_io2_gpio227
73		      &shd_io3_gpio016 >;
74};
75