1 /*
2  * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief CMSIS interface file
10  *
11  * This header contains the interface to the ARM CMSIS Core headers.
12  */
13 
14 #ifndef ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_
15 #define ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_
16 
17 #include <soc.h>
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 #ifndef __CR_REV
24 #define __CR_REV                0U
25 #endif
26 
27 #ifndef __CA_REV
28 #define __CA_REV                0U
29 #endif
30 
31 #ifndef __FPU_PRESENT
32 #define __FPU_PRESENT           CONFIG_CPU_HAS_FPU
33 #endif
34 
35 #ifndef __MMU_PRESENT
36 #define __MMU_PRESENT           CONFIG_CPU_HAS_MMU
37 #endif
38 
39 #ifdef __cplusplus
40 }
41 #endif
42 
43 #if defined(CONFIG_CPU_CORTEX_R4)
44 #include <core_cr4.h>
45 #elif defined(CONFIG_CPU_CORTEX_R5)
46 #include <core_cr5.h>
47 #elif defined(CONFIG_CPU_CORTEX_R7)
48 #include <core_cr7.h>
49 #elif defined(CONFIG_CPU_CORTEX_R52)
50 #include <core_cr52.h>
51 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A)
52 /*
53  * Any defines relevant for the proper inclusion of CMSIS' Cortex-A
54  * Common Peripheral Access Layer (such as __CORTEX_A) which are not
55  * covered by the Kconfig-based default assignments above must be
56  * provided by each aarch32 Cortex-A SoC's header file (already in-
57  * cluded above).
58  */
59 #include <core_ca.h>
60 #else
61 #error "Unknown device"
62 #endif
63 
64 #include "cmsis_core_a_r_ext.h"
65 
66 #endif /* ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_ */
67