1 /* 2 * Copyright (c) 2023 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ 8 9 /** @brief RCC_DCKCFGR register offset */ 10 #define DCKCFGR_REG 0x8C 11 #define DCKCFGR2_REG 0x94 12 13 /** @brief Device domain clocks selection helpers */ 14 /** DCKCFGR devices */ 15 #define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) 16 #define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) 17 #define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) 18 #define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) 19 #define I2S1_SEL(val) STM32_CLOCK(val, 3, 25, DCKCFGR_REG) 20 #define I2S2_SEL(val) STM32_CLOCK(val, 3, 27, DCKCFGR_REG) 21 #define CKDFSDM_SEL(val) STM32_CLOCK(val, 1, 31, DCKCFGR_REG) 22 23 /** DCKCFGR2 devices */ 24 #define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) 25 #define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG) 26 #define SDIO_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG) 27 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 30, DCKCFGR2_REG) 28 29 /* F4 generic I2S_SEL is not compatible with F410 devices */ 30 #ifdef I2S_SEL 31 #undef I2S_SEL 32 #endif 33 34 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */ 35
