1/*
2 * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <freq.h>
8#include <xtensa/xtensa.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
13#include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
14#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
15
16/ {
17
18	aliases {
19		die-temp0 = &coretemp;
20	};
21
22	chosen {
23		zephyr,canbus = &twai;
24		zephyr,entropy = &trng0;
25		zephyr,flash-controller = &flash;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "espressif,xtensa-lx7";
35			reg = <0>;
36			cpu-power-states = <&light_sleep &deep_sleep>;
37			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
38			clock-frequency = <DT_FREQ_M(240)>;
39			xtal-freq = <DT_FREQ_M(40)>;
40		};
41
42		cpu1: cpu@1 {
43			device_type = "cpu";
44			compatible = "espressif,xtensa-lx7";
45			reg = <1>;
46			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
47			clock-frequency = <DT_FREQ_M(240)>;
48			xtal-freq = <DT_FREQ_M(40)>;
49		};
50
51		power-states {
52			light_sleep: light_sleep {
53				compatible = "zephyr,power-state";
54				power-state-name = "standby";
55				min-residency-us = <200>;
56				exit-latency-us = <133>;
57			};
58
59			deep_sleep: deep_sleep {
60				compatible = "zephyr,power-state";
61				power-state-name = "soft-off";
62				min-residency-us = <2000>;
63				exit-latency-us = <382>;
64			};
65		};
66	};
67
68	wifi: wifi {
69		compatible = "espressif,esp32-wifi";
70		status = "disabled";
71	};
72
73	esp32_bt_hci: esp32_bt_hci {
74		compatible = "espressif,esp32-bt-hci";
75		status = "disabled";
76	};
77
78	pinctrl: pin-controller {
79		compatible = "espressif,esp32-pinctrl";
80		status = "okay";
81	};
82
83	soc {
84		#address-cells = <1>;
85		#size-cells = <1>;
86		compatible = "simple-bus";
87		ranges;
88
89		sram0: memory@3fc88000 {
90			compatible = "mmio-sram";
91			reg = <0x3fc88000 0x77FFF>;
92		};
93
94		ipmmem0: memory@3fcbd000 {
95			compatible = "mmio-sram";
96			reg = <0x3fcbd000 0x400>;
97		};
98
99		shm0: memory@3fcbd400 {
100			compatible = "mmio-sram";
101			reg = <0x3fcbd400 0x4000>;
102		};
103
104		intc: interrupt-controller@600c2000 {
105			#interrupt-cells = <1>;
106			compatible = "espressif,esp32-intc";
107			interrupt-controller;
108			reg = <0x600c2000 0x1000>;
109			status = "okay";
110		};
111
112		rtc: rtc@60021000 {
113			compatible = "espressif,esp32-rtc";
114			reg = <0x60021000 0x2000>;
115			fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
116			slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
117			#clock-cells = <1>;
118			status = "okay";
119		};
120
121		xt_wdt: xt_wdt@60021004 {
122			compatible = "espressif,esp32-xt-wdt";
123			reg = <0x60021004 0x4>;
124			clocks = <&rtc ESP32_MODULE_MAX>;
125			interrupts = <RTC_CORE_INTR_SOURCE>;
126			interrupt-parent = <&intc>;
127			status = "disabled";
128		};
129
130		rtc_timer: rtc_timer@60008004 {
131			reg = <0x60008004 0xC>;
132			compatible = "espressif,esp32-rtc-timer";
133			clocks = <&rtc ESP32_MODULE_MAX>;
134			interrupts = <RTC_CORE_INTR_SOURCE>;
135			interrupt-parent = <&intc>;
136			status = "disabled";
137		};
138
139		flash: flash-controller@60002000 {
140			compatible = "espressif,esp32-flash-controller";
141			reg = <0x60002000 0x1000>;
142			/* interrupts = <3 0>; */
143
144			#address-cells = <1>;
145			#size-cells = <1>;
146
147			flash0: flash@0 {
148				compatible = "soc-nv-flash";
149				reg = <0 0x800000>;
150				erase-block-size = <4096>;
151				write-block-size = <4>;
152				/* Flash size is specified in SOC/SIP dtsi */
153			};
154		};
155
156		psram0: psram@3c000000 {
157			device_type = "memory";
158			compatible = "mmio-sram";
159			/* PSRAM size is specified in SOC/SIP dtsi */
160			reg = <0x3c000000 DT_SIZE_M(2)>;
161			status = "disabled";
162		};
163
164		ipm0: ipm@3fcc1400 {
165			compatible = "espressif,esp32-ipm";
166			reg = <0x3fcc1400 0x8>;
167			status = "disabled";
168			shared-memory = <&ipmmem0>;
169			shared-memory-size = <0x400>;
170			interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>;
171			interrupt-parent = <&intc>;
172		};
173
174		uart0: uart@60000000 {
175			compatible = "espressif,esp32-uart";
176			reg = <0x60000000 0x1000>;
177			interrupts = <UART0_INTR_SOURCE>;
178			interrupt-parent = <&intc>;
179			clocks = <&rtc ESP32_UART0_MODULE>;
180			status = "disabled";
181		};
182
183		uart1: uart@60010000 {
184			compatible = "espressif,esp32-uart";
185			reg = <0x60010000 0x1000>;
186			interrupts = <UART1_INTR_SOURCE>;
187			interrupt-parent = <&intc>;
188			clocks = <&rtc ESP32_UART1_MODULE>;
189			status = "disabled";
190		};
191
192		uart2: uart@6002e000 {
193			compatible = "espressif,esp32-uart";
194			reg = <0x6002e000 0x1000>;
195			interrupts = <UART2_INTR_SOURCE>;
196			interrupt-parent = <&intc>;
197			clocks = <&rtc ESP32_UART2_MODULE>;
198			status = "disabled";
199		};
200
201		gpio: gpio {
202			compatible = "simple-bus";
203			gpio-map-mask = <0xffffffe0 0xffffffc0>;
204			gpio-map-pass-thru = <0x1f 0x3f>;
205			gpio-map = <
206				0x00 0x0 &gpio0 0x0 0x0
207				0x20 0x0 &gpio1 0x0 0x0
208			>;
209			#gpio-cells = <2>;
210			#address-cells = <1>;
211			#size-cells = <1>;
212			ranges;
213
214			gpio0: gpio@60004000 {
215				compatible = "espressif,esp32-gpio";
216				gpio-controller;
217				#gpio-cells = <2>;
218				reg = <0x60004000 0x800>;
219				interrupts = <GPIO_INTR_SOURCE>;
220				interrupt-parent = <&intc>;
221				/* Maximum available pins (per port)
222				 * Actual occupied pins are specified
223				 * on part number dtsi level, using
224				 * the `gpio-reserved-ranges` property.
225				 */
226				ngpios = <32>;  /* 0..31 */
227			};
228
229			gpio1: gpio@60004800 {
230				compatible = "espressif,esp32-gpio";
231				gpio-controller;
232				#gpio-cells = <2>;
233				reg = <0x60004800 0x800>;
234				interrupts = <GPIO_INTR_SOURCE>;
235				interrupt-parent = <&intc>;
236				ngpios = <22>; /* 32..53 */
237			};
238		};
239
240		touch: touch@6000885c {
241			compatible = "espressif,esp32-touch";
242			reg = <0x6000885c 0x88 0x60008908 0x18>;
243			interrupts = <RTC_CORE_INTR_SOURCE>;
244			interrupt-parent = <&intc>;
245			status = "disabled";
246		};
247
248		i2c0: i2c@60013000 {
249			compatible = "espressif,esp32-i2c";
250			#address-cells = <1>;
251			#size-cells = <0>;
252			reg = <0x60013000 DT_SIZE_K(4)>;
253			interrupts = <I2C_EXT0_INTR_SOURCE>;
254			interrupt-parent = <&intc>;
255			clocks = <&rtc ESP32_I2C0_MODULE>;
256			status = "disabled";
257		};
258
259		i2c1: i2c@60027000 {
260			compatible = "espressif,esp32-i2c";
261			#address-cells = <1>;
262			#size-cells = <0>;
263			reg = <0x60027000 DT_SIZE_K(4)>;
264			interrupts = <I2C_EXT1_INTR_SOURCE>;
265			interrupt-parent = <&intc>;
266			clocks = <&rtc ESP32_I2C1_MODULE>;
267			status = "disabled";
268		};
269
270		spi2: spi@60024000 {
271			compatible = "espressif,esp32-spi";
272			reg = <0x60024000 DT_SIZE_K(4)>;
273			interrupts = <SPI2_INTR_SOURCE>;
274			interrupt-parent = <&intc>;
275			clocks = <&rtc ESP32_SPI2_MODULE>;
276			dma-clk = <ESP32_GDMA_MODULE>;
277			dma-host = <0>;
278			status = "disabled";
279		};
280
281		spi3: spi@60025000 {
282			compatible = "espressif,esp32-spi";
283			reg = <0x60025000 DT_SIZE_K(4)>;
284			interrupts = <SPI3_INTR_SOURCE>;
285			interrupt-parent = <&intc>;
286			clocks = <&rtc ESP32_SPI3_MODULE>;
287			dma-clk = <ESP32_GDMA_MODULE>;
288			dma-host = <1>;
289			status = "disabled";
290		};
291
292		coretemp: coretemp@60008800 {
293			compatible = "espressif,esp32-temp";
294			friendly-name = "coretemp";
295			reg = <0x60008800 0x4>;
296			status = "disabled";
297		};
298
299		adc0: adc@60040000 {
300			compatible = "espressif,esp32-adc";
301			reg = <0x60040000 4>;
302			unit = <1>;
303			channel-count = <10>;
304			#io-channel-cells = <1>;
305			status = "disabled";
306		};
307
308		adc1: adc@60040004 {
309			compatible = "espressif,esp32-adc";
310			reg = <0x60040004 4>;
311			unit = <2>;
312			channel-count = <10>;
313			#io-channel-cells = <1>;
314			status = "disabled";
315		};
316
317		twai: can@6002b000 {
318			compatible = "espressif,esp32-twai";
319			reg = <0x6002b000 DT_SIZE_K(4)>;
320			interrupts = <TWAI_INTR_SOURCE>;
321			interrupt-parent = <&intc>;
322			clocks = <&rtc ESP32_TWAI_MODULE>;
323			status = "disabled";
324		};
325
326		usb_serial: uart@60038000 {
327			compatible = "espressif,esp32-usb-serial";
328			reg = <0x60038000 DT_SIZE_K(4)>;
329			status = "disabled";
330			interrupts = <USB_SERIAL_JTAG_INTR_SOURCE>;
331			interrupt-parent = <&intc>;
332			clocks = <&rtc ESP32_USB_MODULE>;
333		};
334
335		timer0: counter@6001f000 {
336			compatible = "espressif,esp32-timer";
337			reg = <0x6001f000 DT_SIZE_K(4)>;
338			group = <0>;
339			index = <0>;
340			interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
341			interrupt-parent = <&intc>;
342			status = "disabled";
343		};
344
345		timer1: counter@6001f024 {
346			compatible = "espressif,esp32-timer";
347			reg = <0x6001f024 DT_SIZE_K(4)>;
348			group = <0>;
349			index = <1>;
350			interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
351			interrupt-parent = <&intc>;
352			status = "disabled";
353		};
354
355		timer2: counter@60020000 {
356			compatible = "espressif,esp32-timer";
357			reg = <0x60020000 DT_SIZE_K(4)>;
358			group = <1>;
359			index = <0>;
360			interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
361			interrupt-parent = <&intc>;
362			status = "disabled";
363		};
364
365		timer3: counter@60020024 {
366			compatible = "espressif,esp32-timer";
367			reg = <0x60020024 DT_SIZE_K(4)>;
368			group = <1>;
369			index = <1>;
370			interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
371			interrupt-parent = <&intc>;
372		};
373
374		wdt0: watchdog@6001f048 {
375			compatible = "espressif,esp32-watchdog";
376			reg = <0x6001f048 0x20>;
377			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
378			interrupt-parent = <&intc>;
379			clocks = <&rtc ESP32_TIMG0_MODULE>;
380			status = "disabled";
381		};
382
383		wdt1: watchdog@60020048 {
384			compatible = "espressif,esp32-watchdog";
385			reg = <0x60020048 0x20>;
386			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
387			interrupt-parent = <&intc>;
388			clocks = <&rtc ESP32_TIMG1_MODULE>;
389			status = "disabled";
390		};
391
392		trng0: trng@6003507c {
393			compatible = "espressif,esp32-trng";
394			reg = <0x6003507c 0x4>;
395			status = "disabled";
396		};
397
398		ledc0: ledc@60019000 {
399			compatible = "espressif,esp32-ledc";
400			#pwm-cells = <3>;
401			reg = <0x60019000 DT_SIZE_K(4)>;
402			clocks = <&rtc ESP32_LEDC_MODULE>;
403			status = "disabled";
404		};
405
406		mcpwm0: mcpwm@6001e000 {
407			compatible = "espressif,esp32-mcpwm";
408			reg = <0x6001e000 DT_SIZE_K(4)>;
409			interrupts = <PWM0_INTR_SOURCE>;
410			interrupt-parent = <&intc>;
411			clocks = <&rtc ESP32_PWM0_MODULE>;
412			#pwm-cells = <3>;
413			status = "disabled";
414		};
415
416		mcpwm1: mcpwm@6002c000 {
417			compatible = "espressif,esp32-mcpwm";
418			reg = <0x6002c000 DT_SIZE_K(4)>;
419			interrupts = <PWM1_INTR_SOURCE>;
420			interrupt-parent = <&intc>;
421			clocks = <&rtc ESP32_PWM1_MODULE>;
422			#pwm-cells = <3>;
423			status = "disabled";
424		};
425
426		pcnt: pcnt@60017000 {
427			compatible = "espressif,esp32-pcnt";
428			reg = <0x60017000 DT_SIZE_K(4)>;
429			interrupts = <PCNT_INTR_SOURCE>;
430			interrupt-parent = <&intc>;
431			clocks = <&rtc ESP32_PCNT_MODULE>;
432			status = "disabled";
433		};
434
435		dma: dma@6003f000 {
436			compatible = "espressif,esp32-gdma";
437			reg = <0x6003f000 DT_SIZE_K(4)>;
438			#dma-cells = <1>;
439			interrupts = <DMA_IN_CH0_INTR_SOURCE DMA_OUT_CH0_INTR_SOURCE
440						DMA_IN_CH1_INTR_SOURCE DMA_OUT_CH1_INTR_SOURCE
441						DMA_IN_CH2_INTR_SOURCE DMA_OUT_CH2_INTR_SOURCE>;
442			interrupt-parent = <&intc>;
443			clocks = <&rtc ESP32_GDMA_MODULE>;
444			dma-channels = <10>;
445			dma-buf-addr-alignment = <4>;
446			status = "disabled";
447		};
448
449	};
450};
451