1/* 2 * Copyright (c) 2019 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <mem.h> 7#include <freq.h> 8#include <xtensa/xtensa.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/clock/esp32_clock.h> 13#include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h> 14#include <dt-bindings/pinctrl/esp32-pinctrl.h> 15#include <zephyr/dt-bindings/pwm/pwm.h> 16 17/ { 18 chosen { 19 zephyr,canbus = &twai; 20 zephyr,entropy = &trng0; 21 zephyr,flash-controller = &flash; 22 zephyr,bt-hci = &esp32_bt_hci; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "espressif,xtensa-lx6"; 32 reg = <0>; 33 cpu-power-states = <&light_sleep &deep_sleep>; 34 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 35 clock-frequency = <DT_FREQ_M(240)>; 36 xtal-freq = <DT_FREQ_M(40)>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "espressif,xtensa-lx6"; 42 reg = <1>; 43 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 44 clock-frequency = <DT_FREQ_M(240)>; 45 xtal-freq = <DT_FREQ_M(40)>; 46 }; 47 48 power-states { 49 light_sleep: light_sleep { 50 compatible = "zephyr,power-state"; 51 power-state-name = "standby"; 52 min-residency-us = <200>; 53 exit-latency-us = <60>; 54 }; 55 56 deep_sleep: deep_sleep { 57 compatible = "zephyr,power-state"; 58 power-state-name = "soft-off"; 59 min-residency-us = <2000>; 60 exit-latency-us = <212>; 61 }; 62 }; 63 }; 64 65 wifi: wifi { 66 compatible = "espressif,esp32-wifi"; 67 status = "disabled"; 68 }; 69 70 esp32_bt_hci: esp32_bt_hci { 71 compatible = "espressif,esp32-bt-hci"; 72 status = "disabled"; 73 }; 74 75 eth: eth { 76 compatible = "espressif,esp32-eth"; 77 interrupts = <ETH_MAC_INTR_SOURCE>; 78 interrupt-parent = <&intc>; 79 clocks = <&rtc ESP32_EMAC_MODULE>; 80 status = "disabled"; 81 }; 82 83 mdio: mdio { 84 compatible = "espressif,esp32-mdio"; 85 clocks = <&rtc ESP32_EMAC_MODULE>; 86 status = "disabled"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 }; 90 91 pinctrl: pin-controller { 92 compatible = "espressif,esp32-pinctrl"; 93 status = "okay"; 94 }; 95 96 soc { 97 sram0: memory@3ffb0000 { 98 compatible = "mmio-sram"; 99 reg = <0x3FFB0000 0x2c200>; 100 }; 101 102 ipmmem0: memory@3ffe5230 { 103 compatible = "mmio-sram"; 104 reg = <0x3FFE5230 0x400>; 105 }; 106 107 shm0: memory@3ffe5630 { 108 compatible = "mmio-sram"; 109 reg = <0x3FFE5630 0x3C00>; 110 }; 111 112 intc: interrupt-controller@3ff00104 { 113 #interrupt-cells = <1>; 114 compatible = "espressif,esp32-intc"; 115 interrupt-controller; 116 reg = <0x3ff00104 0x114>; 117 status = "okay"; 118 }; 119 120 rtc: rtc@3ff48000 { 121 compatible = "espressif,esp32-rtc"; 122 reg = <0x3ff48000 0x0D8>; 123 fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>; 124 slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>; 125 #clock-cells = <1>; 126 status = "okay"; 127 128 }; 129 130 rtc_timer: rtc_timer@3ff48004 { 131 reg = <0x3ff48004 0xC>; 132 compatible = "espressif,esp32-rtc-timer"; 133 clocks = <&rtc ESP32_MODULE_MAX>; 134 interrupts = <RTC_CORE_INTR_SOURCE>; 135 interrupt-parent = <&intc>; 136 status = "okay"; 137 }; 138 139 flash: flash-controller@3ff42000 { 140 compatible = "espressif,esp32-flash-controller"; 141 reg = <0x3ff42000 0x1000>; 142 /* interrupts = <3 0>; */ 143 144 #address-cells = <1>; 145 #size-cells = <1>; 146 147 flash0: flash@0 { 148 compatible = "soc-nv-flash"; 149 erase-block-size = <4096>; 150 write-block-size = <4>; 151 /* Flash size is specified in SOC/SIP dtsi */ 152 }; 153 }; 154 155 psram0: psram@3f800000 { 156 device_type = "memory"; 157 compatible = "mmio-sram"; 158 /* PSRAM size is specified in SOC/SIP dtsi */ 159 reg = <0x3f800000 DT_SIZE_M(2)>; 160 status = "disabled"; 161 }; 162 163 ipm0: ipm@3ffed238 { 164 compatible = "espressif,esp32-ipm"; 165 reg = <0x3FFED238 0x8>; 166 status = "disabled"; 167 shared-memory = <&ipmmem0>; 168 shared-memory-size = <0x400>; 169 interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>; 170 interrupt-parent = <&intc>; 171 }; 172 173 ipi0: ipi@3f4c0058 { 174 compatible = "espressif,crosscore-interrupt"; 175 reg = <0x3f4c0058 0x4>; 176 interrupts = <FROM_CPU_INTR0_SOURCE>; 177 interrupt-parent = <&intc>; 178 }; 179 180 ipi1: ipi@3f4c005c { 181 compatible = "espressif,crosscore-interrupt"; 182 reg = <0x3f4c005c 0x4>; 183 interrupts = <FROM_CPU_INTR1_SOURCE>; 184 interrupt-parent = <&intc>; 185 }; 186 187 uart0: uart@3ff40000 { 188 compatible = "espressif,esp32-uart"; 189 reg = <0x3ff40000 0x400>; 190 interrupts = <UART0_INTR_SOURCE>; 191 interrupt-parent = <&intc>; 192 clocks = <&rtc ESP32_UART0_MODULE>; 193 status = "disabled"; 194 }; 195 196 uart1: uart@3ff50000 { 197 compatible = "espressif,esp32-uart"; 198 reg = <0x3ff50000 0x400>; 199 interrupts = <UART1_INTR_SOURCE>; 200 interrupt-parent = <&intc>; 201 clocks = <&rtc ESP32_UART1_MODULE>; 202 status = "disabled"; 203 }; 204 205 uart2: uart@3ff6e000 { 206 compatible = "espressif,esp32-uart"; 207 reg = <0x3ff6E000 0x400>; 208 interrupts = <UART2_INTR_SOURCE>; 209 interrupt-parent = <&intc>; 210 clocks = <&rtc ESP32_UART2_MODULE>; 211 status = "disabled"; 212 }; 213 214 pcnt: pcnt@3ff57000 { 215 compatible = "espressif,esp32-pcnt"; 216 reg = <0x3ff57000 0x1000>; 217 interrupts = <PCNT_INTR_SOURCE>; 218 interrupt-parent = <&intc>; 219 clocks = <&rtc ESP32_PCNT_MODULE>; 220 status = "disabled"; 221 }; 222 223 ledc0: ledc@3ff59000 { 224 compatible = "espressif,esp32-ledc"; 225 #pwm-cells = <3>; 226 reg = <0x3ff59000 0x800>; 227 clocks = <&rtc ESP32_LEDC_MODULE>; 228 status = "disabled"; 229 }; 230 231 mcpwm0: mcpwm@3ff5e000 { 232 compatible = "espressif,esp32-mcpwm"; 233 reg = <0x3ff5e000 0x1000>; 234 interrupts = <PWM0_INTR_SOURCE>; 235 interrupt-parent = <&intc>; 236 clocks = <&rtc ESP32_PWM0_MODULE>; 237 #pwm-cells = <3>; 238 status = "disabled"; 239 }; 240 241 mcpwm1: mcpwm@3ff6c000 { 242 compatible = "espressif,esp32-mcpwm"; 243 reg = <0x3ff6c000 0x1000>; 244 interrupts = <PWM1_INTR_SOURCE>; 245 interrupt-parent = <&intc>; 246 clocks = <&rtc ESP32_PWM1_MODULE>; 247 #pwm-cells = <3>; 248 status = "disabled"; 249 }; 250 251 gpio: gpio { 252 compatible = "simple-bus"; 253 gpio-map-mask = <0xffffffe0 0xffffffc0>; 254 gpio-map-pass-thru = <0x1f 0x3f>; 255 gpio-map = < 256 0x00 0x0 &gpio0 0x0 0x0 257 0x20 0x0 &gpio1 0x0 0x0 258 >; 259 #gpio-cells = <2>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges; 263 264 gpio0: gpio@3ff44000 { 265 compatible = "espressif,esp32-gpio"; 266 gpio-controller; 267 #gpio-cells = <2>; 268 reg = <0x3ff44000 0x800>; 269 interrupts = <GPIO_INTR_SOURCE>; 270 interrupt-parent = <&intc>; 271 /* Maximum available pins (per port) 272 * Actual occupied pins are specified 273 * on part number dtsi level, using 274 * the `gpio-reserved-ranges` property. 275 */ 276 ngpios = <32>; /* 0..31 */ 277 }; 278 279 gpio1: gpio@3ff44800 { 280 compatible = "espressif,esp32-gpio"; 281 gpio-controller; 282 #gpio-cells = <2>; 283 reg = <0x3ff44800 0x800>; 284 interrupts = <GPIO_INTR_SOURCE>; 285 interrupt-parent = <&intc>; 286 ngpios = <8>; /* 32..39 */ 287 }; 288 }; 289 290 touch: touch@3ff48858 { 291 compatible = "espressif,esp32-touch"; 292 reg = <0x3ff48858 0x38>; 293 interrupts = <RTC_CORE_INTR_SOURCE>; 294 interrupt-parent = <&intc>; 295 status = "disabled"; 296 }; 297 298 i2c0: i2c@3ff53000 { 299 compatible = "espressif,esp32-i2c"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 reg = <0x3ff53000 0x1000>; 303 interrupts = <I2C_EXT0_INTR_SOURCE>; 304 interrupt-parent = <&intc>; 305 clocks = <&rtc ESP32_I2C0_MODULE>; 306 status = "disabled"; 307 }; 308 309 i2c1: i2c@3ff67000 { 310 compatible = "espressif,esp32-i2c"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 reg = <0x3ff67000 0x1000>; 314 interrupts = <I2C_EXT1_INTR_SOURCE>; 315 interrupt-parent = <&intc>; 316 clocks = <&rtc ESP32_I2C1_MODULE>; 317 status = "disabled"; 318 }; 319 320 trng0: trng@3ff75144 { 321 compatible = "espressif,esp32-trng"; 322 reg = <0x3FF75144 0x4>; 323 /* interrupts = <33 0>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */ 324 status = "disabled"; 325 }; 326 327 wdt0: watchdog@3ff5f048 { 328 compatible = "espressif,esp32-watchdog"; 329 reg = <0x3ff5f048 0x20>; 330 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>; 331 interrupt-parent = <&intc>; 332 clocks = <&rtc ESP32_TIMG0_MODULE>; 333 status = "okay"; 334 }; 335 336 wdt1: watchdog@3ff60048 { 337 compatible = "espressif,esp32-watchdog"; 338 reg = <0x3ff60048 0x20>; 339 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>; 340 interrupt-parent = <&intc>; 341 clocks = <&rtc ESP32_TIMG1_MODULE>; 342 status = "disabled"; 343 }; 344 345 spi2: spi@3ff64000 { 346 compatible = "espressif,esp32-spi"; 347 reg = <0x3ff64000 DT_SIZE_K(4)>; 348 interrupts = <SPI2_INTR_SOURCE>; 349 interrupt-parent = <&intc>; 350 clocks = <&rtc ESP32_HSPI_MODULE>; 351 dma-clk = <ESP32_SPI_DMA_MODULE>; 352 dma-host = <0>; 353 status = "disabled"; 354 }; 355 356 spi3: spi@3ff65000 { 357 compatible = "espressif,esp32-spi"; 358 reg = <0x3ff65000 DT_SIZE_K(4)>; 359 interrupts = <SPI3_INTR_SOURCE>; 360 interrupt-parent = <&intc>; 361 clocks = <&rtc ESP32_VSPI_MODULE>; 362 dma-clk = <ESP32_SPI_DMA_MODULE>; 363 dma-host = <1>; 364 status = "disabled"; 365 }; 366 367 twai: can@3ff6b000 { 368 compatible = "espressif,esp32-twai"; 369 reg = <0x3ff6b000 DT_SIZE_K(4)>; 370 interrupts = <TWAI_INTR_SOURCE>; 371 interrupt-parent = <&intc>; 372 clocks = <&rtc ESP32_TWAI_MODULE>; 373 status = "disabled"; 374 }; 375 376 timer0: counter@3ff5f000 { 377 compatible = "espressif,esp32-timer"; 378 reg = <0x3ff5f000 DT_SIZE_K(4)>; 379 group = <0>; 380 index = <0>; 381 interrupts = <TG0_T0_LEVEL_INTR_SOURCE>; 382 interrupt-parent = <&intc>; 383 status = "disabled"; 384 }; 385 386 timer1: counter@3ff5f024 { 387 compatible = "espressif,esp32-timer"; 388 reg = <0x3ff5f024 DT_SIZE_K(4)>; 389 group = <0>; 390 index = <1>; 391 interrupts = <TG0_T1_LEVEL_INTR_SOURCE>; 392 interrupt-parent = <&intc>; 393 status = "disabled"; 394 }; 395 396 timer2: counter@3ff60000 { 397 compatible = "espressif,esp32-timer"; 398 reg = <0x3ff60000 DT_SIZE_K(4)>; 399 group = <1>; 400 index = <0>; 401 interrupts = <TG1_T0_LEVEL_INTR_SOURCE>; 402 interrupt-parent = <&intc>; 403 status = "disabled"; 404 }; 405 406 timer3: counter@3ff60024 { 407 compatible = "espressif,esp32-timer"; 408 reg = <0x3ff60024 DT_SIZE_K(4)>; 409 group = <1>; 410 index = <1>; 411 interrupts = <TG1_T1_LEVEL_INTR_SOURCE>; 412 interrupt-parent = <&intc>; 413 status = "disabled"; 414 }; 415 416 dac: dac@3ff48800 { 417 compatible = "espressif,esp32-dac"; 418 reg = <0x3ff48800 0x100>; 419 interrupts = <RTC_CORE_INTR_SOURCE>; 420 interrupt-parent = <&intc>; 421 clocks = <&rtc ESP32_SARADC_MODULE>; 422 #io-channel-cells = <1>; 423 status = "disabled"; 424 }; 425 426 adc0: adc@3ff48800 { 427 compatible = "espressif,esp32-adc"; 428 reg = <0x3ff48800 10>; 429 unit = <1>; 430 channel-count = <8>; 431 #io-channel-cells = <1>; 432 status = "disabled"; 433 }; 434 435 adc1: adc@3ff48890 { 436 compatible = "espressif,esp32-adc"; 437 reg = <0x3ff48890 10>; 438 unit = <2>; 439 channel-count = <10>; 440 #io-channel-cells = <1>; 441 status = "disabled"; 442 }; 443 444 sdhc: sdhc@3ff68000 { 445 compatible = "espressif,esp32-sdhc"; 446 reg = <0x3ff68000 0x1000>; 447 interrupts = <SDIO_HOST_INTR_SOURCE>; 448 interrupt-parent = <&intc>; 449 clocks = <&rtc ESP32_SDMMC_MODULE>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 sdhc0: sdhc@0 { 454 compatible = "espressif,esp32-sdhc-slot"; 455 reg = <0>; 456 status = "disabled"; 457 }; 458 459 sdhc1: sdhc@1 { 460 compatible = "espressif,esp32-sdhc-slot"; 461 reg = <1>; 462 status = "disabled"; 463 }; 464 }; 465 }; 466}; 467
