1/*
2 * Copyright (c) 2023 Intel Corporation.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include "skeleton.dtsi"
7#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8#include <zephyr/dt-bindings/pcie/pcie.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			compatible = "intel,raptor-lake";
19			device_type = "cpu";
20			d-cache-line-size = <64>;
21			reg = <0>;
22		};
23	};
24
25	dram0: memory@0 {
26		device_type = "memory";
27		reg = <0x0 DT_DRAM_SIZE>;
28	};
29
30	intc: ioapic@fec00000  {
31		compatible = "intel,ioapic";
32		reg = <0xfec00000 0x1000>;
33		interrupt-controller;
34		#interrupt-cells = <3>;
35	};
36
37	intc_loapic: loapic@fee00000  {
38		compatible = "intel,loapic";
39		reg = <0xfee00000 0x1000>;
40		interrupt-controller;
41		#interrupt-cells = <3>;
42		#address-cells = <1>;
43	};
44
45	pcie0: pcie0 {
46		compatible = "pcie-controller";
47		#address-cells = <1>;
48		#size-cells = <1>;
49		acpi-hid = "PNP0A08";
50		ranges;
51
52		smbus0: smbus0 {
53			compatible = "intel,pch-smbus";
54			#address-cells = <1>;
55			#size-cells = <0>;
56			vendor-id = <0x8086>;
57			device-id = <0x51a3>;
58			interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
59			interrupt-parent = <&intc>;
60
61			status = "okay";
62		};
63
64		uart0: uart0 {
65			compatible = "ns16550";
66			vendor-id = <0x8086>;
67			device-id = <0x51a8>;
68			reg-shift = <2>;
69			clock-frequency = <1843200>;
70			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
71			interrupt-parent = <&intc>;
72			current-speed = <115200>;
73
74			status = "okay";
75		};
76
77		uart1: uart1 {
78			compatible = "ns16550";
79			vendor-id = <0x8086>;
80			device-id = <0x51A9>;
81			reg-shift = <2>;
82			clock-frequency = <1843200>;
83			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
84			interrupt-parent = <&intc>;
85			current-speed = <115200>;
86
87			status = "okay";
88		};
89
90		spi0: spi0 {
91			compatible = "intel,penwell-spi";
92			#address-cells = <1>;
93			#size-cells = <0>;
94			vendor-id = <0x8086>;
95			device-id = <0x51aa>;
96			pw,cs-mode = <0>;
97			pw,cs-output = <0>;
98			pw,fifo-depth = <64>;
99			cs-gpios = <&gpio_4_e 10 GPIO_ACTIVE_LOW>;
100			clock-frequency = <100000000>;
101			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
102			interrupt-parent = <&intc>;
103
104			status = "okay";
105		};
106
107		spi1: spi1 {
108			compatible = "intel,penwell-spi";
109			#address-cells = <1>;
110			#size-cells = <0>;
111			vendor-id = <0x8086>;
112			device-id = <0x51ab>;
113			pw,cs-mode = <0>;
114			pw,cs-output = <0>;
115			pw,fifo-depth = <64>;
116			cs-gpios = <&gpio_4_f 16 GPIO_ACTIVE_LOW>;
117			clock-frequency = <100000000>;
118			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
119			interrupt-parent = <&intc>;
120
121			status = "disabled";
122		};
123
124		spi2: spi2 {
125			compatible = "intel,penwell-spi";
126			#address-cells = <1>;
127			#size-cells = <0>;
128			vendor-id = <0x8086>;
129			device-id = <0x51fb>;
130			pw,cs-mode = <0>;
131			pw,cs-output = <0>;
132			pw,fifo-depth = <64>;
133			cs-gpios = <&gpio_1_d 9 GPIO_ACTIVE_LOW>;
134			clock-frequency = <100000000>;
135			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
136			interrupt-parent = <&intc>;
137
138			status = "disabled";
139		};
140
141		i2c0: i2c0 {
142			compatible = "snps,designware-i2c";
143			#address-cells = <1>;
144			#size-cells = <0>;
145			clock-frequency = <I2C_BITRATE_STANDARD>;
146			vendor-id = <0x8086>;
147			device-id = <0x51e8>;
148			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
149			interrupt-parent = <&intc>;
150
151			status = "okay";
152		};
153
154		i2c1: i2c1 {
155			compatible = "snps,designware-i2c";
156			#address-cells = <1>;
157			#size-cells = <0>;
158			clock-frequency = <I2C_BITRATE_STANDARD>;
159			vendor-id = <0x8086>;
160			device-id = <0x51e9>;
161			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
162			interrupt-parent = <&intc>;
163
164			status = "okay";
165		};
166
167		i2c2: i2c2 {
168			compatible = "snps,designware-i2c";
169			#address-cells = <1>;
170			#size-cells = <0>;
171			clock-frequency = <I2C_BITRATE_STANDARD>;
172			vendor-id = <0x8086>;
173			device-id = <0x51ea>;
174			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
175			interrupt-parent = <&intc>;
176
177			status = "disabled";
178		};
179
180		i2c3: i2c3 {
181			compatible = "snps,designware-i2c";
182			#address-cells = <1>;
183			#size-cells = <0>;
184			clock-frequency = <I2C_BITRATE_STANDARD>;
185			vendor-id = <0x8086>;
186			device-id = <0x51eb>;
187			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
188			interrupt-parent = <&intc>;
189
190			status = "disabled";
191		};
192
193		i2c4: i2c4 {
194			compatible = "snps,designware-i2c";
195			#address-cells = <1>;
196			#size-cells = <0>;
197			clock-frequency = <I2C_BITRATE_STANDARD>;
198			vendor-id = <0x8086>;
199			device-id = <0x51c5>;
200			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
201			interrupt-parent = <&intc>;
202
203			status = "disabled";
204		};
205
206		i2c5: i2c5 {
207			compatible = "snps,designware-i2c";
208			#address-cells = <1>;
209			#size-cells = <0>;
210			clock-frequency = <I2C_BITRATE_STANDARD>;
211			vendor-id = <0x8086>;
212			device-id = <0x51c6>;
213			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
214			interrupt-parent = <&intc>;
215
216			status = "disabled";
217		};
218
219		i2c6: i2c6 {
220			compatible = "snps,designware-i2c";
221			#address-cells = <1>;
222			#size-cells = <0>;
223			clock-frequency = <I2C_BITRATE_STANDARD>;
224			vendor-id = <0x8086>;
225			device-id = <0x51d8>;
226			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
227			interrupt-parent = <&intc>;
228
229			status = "disabled";
230		};
231
232		i2c7: i2c7 {
233			compatible = "snps,designware-i2c";
234			#address-cells = <1>;
235			#size-cells = <0>;
236			clock-frequency = <I2C_BITRATE_STANDARD>;
237			vendor-id = <0x8086>;
238			device-id = <0x51d9>;
239			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
240			interrupt-parent = <&intc>;
241
242			status = "disabled";
243		};
244	};
245
246	soc {
247		compatible = "simple-bus";
248		#address-cells = <1>;
249		#size-cells = <1>;
250		ranges;
251
252		gpio_0_b: gpio@fd6e0700 {
253			compatible = "intel,gpio";
254			reg = <0xfd6e0700 0x1000>;
255			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
256			interrupt-parent = <&intc>;
257
258			group-index = <0x0>;
259			gpio-controller;
260			#gpio-cells = <2>;
261
262			ngpios = <24>;
263			pin-offset = <0>;
264
265			status = "okay";
266		};
267
268		gpio_0_t: gpio@fd6e08a0 {
269			compatible = "intel,gpio";
270			reg = <0xfd6e08a0 0x1000>;
271			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
272			interrupt-parent = <&intc>;
273
274			group-index = <0x1>;
275			gpio-controller;
276			#gpio-cells = <2>;
277
278			ngpios = <4>;
279			pin-offset = <25>;
280
281			status = "okay";
282		};
283
284		gpio_0_a: gpio@fd6e09a0 {
285			compatible = "intel,gpio";
286			reg = <0xfd6e09a0 0x1000>;
287			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
288			interrupt-parent = <&intc>;
289
290			group-index = <0x2>;
291			gpio-controller;
292			#gpio-cells = <2>;
293
294			ngpios = <24>;
295			pin-offset = <41>;
296
297			status = "okay";
298		};
299
300		gpio_1_s: gpio@fd6d0700 {
301			compatible = "intel,gpio";
302			reg = <0xfd6d0700 0x1000>;
303			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
304			interrupt-parent = <&intc>;
305
306			group-index = <0x0>;
307			gpio-controller;
308			#gpio-cells = <2>;
309
310			ngpios = <8>;
311			pin-offset = <0>;
312
313			status = "okay";
314		};
315
316		gpio_1_h: gpio@fd6d0780 {
317			compatible = "intel,gpio";
318			reg = <0xfd6d0780 0x1000>;
319			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
320			interrupt-parent = <&intc>;
321
322			group-index = <0x1>;
323			gpio-controller;
324			#gpio-cells = <2>;
325
326			ngpios = <24>;
327			pin-offset = <8>;
328
329			status = "okay";
330		};
331
332
333		gpio_1_d: gpio@fd6d0900 {
334			compatible = "intel,gpio";
335			reg = <0xfd6d0900 0x1000>;
336			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
337			interrupt-parent = <&intc>;
338
339			group-index = <0x2>;
340			gpio-controller;
341			#gpio-cells = <2>;
342
343			ngpios = <20>;
344			pin-offset = <25>;
345
346			status = "okay";
347		};
348
349		gpio_2_gpd: gpio@fd6c0700 {
350			compatible = "intel,gpio";
351			reg = <0xfd6c0700 0x1000>;
352			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
353			interrupt-parent = <&intc>;
354
355			group-index = <0x0>;
356			gpio-controller;
357			#gpio-cells = <2>;
358
359			ngpios = <12>;
360			pin-offset = <0>;
361
362			status = "okay";
363		};
364
365		gpio_4_c: gpio@fd6a0700 {
366			compatible = "intel,gpio";
367			reg = <0xfd6a0700 0x1000>;
368			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
369			interrupt-parent = <&intc>;
370
371			group-index = <0x0>;
372			gpio-controller;
373			#gpio-cells = <2>;
374
375			ngpios = <24>;
376			pin-offset = <0>;
377
378			status = "okay";
379		};
380
381		gpio_4_f: gpio@fd6a0880 {
382			compatible = "intel,gpio";
383			reg = <0xfd6a0880 0x1000>;
384			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
385			interrupt-parent = <&intc>;
386
387			group-index = <0x1>;
388			gpio-controller;
389			#gpio-cells = <2>;
390
391			ngpios = <24>;
392			pin-offset = <24>;
393
394			status = "okay";
395		};
396
397		gpio_4_e: gpio@fd6a0a70 {
398			compatible = "intel,gpio";
399			reg = <0xfd6a0a70 0x1000>;
400			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
401			interrupt-parent = <&intc>;
402
403			group-index = <0x3>;
404			gpio-controller;
405			#gpio-cells = <2>;
406
407			ngpios = <24>;
408			pin-offset = <57>;
409
410			status = "okay";
411		};
412
413		gpio_5_r: gpio@fd690700 {
414			compatible = "intel,gpio";
415			reg = <0xfd690700 0x1000>;
416			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
417			interrupt-parent = <&intc>;
418
419			group-index = <0x0>;
420			gpio-controller;
421			#gpio-cells = <2>;
422
423			ngpios = <8>;
424			pin-offset = <0>;
425
426			status = "okay";
427		};
428
429		tgpio: tgpio@fe001200 {
430			compatible = "intel,timeaware-gpio";
431			reg = <0xfe001200 0x100>;
432			timer-clock = <19200000>;
433			max-pins = <2>;
434
435			status = "okay";
436		};
437
438		rtc: counter: rtc@70 {
439			compatible = "motorola,mc146818";
440			reg = <0x70 0x0D 0x71 0x0D>;
441			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
442			interrupt-parent = <&intc>;
443			alarms-count = <1>;
444
445			status = "okay";
446		};
447
448		hpet: hpet@fed00000 {
449			compatible = "intel,hpet";
450			reg = <0xfed00000 0x400>;
451			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
452			interrupt-parent = <&intc>;
453
454			status = "okay";
455		};
456
457		tco_wdt: tco_wdt@400 {
458			compatible = "intel,tco-wdt";
459			reg = <0x0400 0x20>;
460
461			status = "disabled";
462		};
463
464		pwm0: pwm0@fd6d0000 {
465			compatible = "intel,blinky-pwm";
466			reg = <0xfd6d0000 0x400>;
467			reg-offset = <0x204>;
468			clock-frequency = <32768>;
469			max-pins = <1>;
470			#pwm-cells = <2>;
471
472			status = "okay";
473		};
474	};
475};
476