1/* 2 * Copyright (c) 2021 Telink Semiconductor 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/adc/b91-adc.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 cpu0: cpu@0 { 23 reg = <0>; 24 clock-frequency = <24000000>; 25 compatible ="telink,b91", "riscv"; 26 riscv,isa = "rv32imac_zicsr_zifencei"; 27 hlic: interrupt-controller { 28 compatible = "riscv,cpu-intc"; 29 #address-cells = <0>; 30 #interrupt-cells = <1>; 31 interrupt-controller; 32 }; 33 }; 34 }; 35 36 soc { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 compatible = "telink,telink_b91-soc"; 40 ranges; 41 42 ram_ilm: memory@0 { 43 compatible = "mmio-sram"; 44 }; 45 46 ram_dlm: memory@80000 { 47 compatible = "mmio-sram"; 48 }; 49 50 mtimer: timer@e6000000 { 51 compatible = "telink,machine-timer"; 52 reg = <0xe6000000 0x10000>; 53 interrupts = <7 0>; 54 interrupt-parent = <&plic0>; 55 }; 56 57 flash_mspi: flash-controller@80140100 { 58 compatible = "telink,b91-flash-controller"; 59 reg = <0x80140100 0x40>; 60 61 #address-cells = <1>; 62 #size-cells = <1>; 63 64 flash: flash@20000000 { 65 compatible = "soc-nv-flash"; 66 write-block-size = <1>; 67 }; 68 }; 69 70 power: power@80140180 { 71 compatible = "telink,b91-power"; 72 reg = <0x80140180 0x40>; 73 power-mode = "LDO_1P4_LDO_1P8"; 74 vbat-type = "VBAT_MAX_VALUE_GREATER_THAN_3V6"; 75 status = "okay"; 76 }; 77 78 gpioa: gpio@80140300 { 79 compatible = "telink,b91-gpio"; 80 gpio-controller; 81 interrupt-parent = <&plic0>; 82 interrupts = <25 1>, <26 1>, <27 1>; 83 reg = <0x80140300 0x08>; 84 status = "disabled"; 85 #gpio-cells = <2>; 86 }; 87 88 gpiob: gpio@80140308 { 89 compatible = "telink,b91-gpio"; 90 gpio-controller; 91 interrupt-parent = <&plic0>; 92 interrupts = <25 1>, <26 1>, <27 1>; 93 reg = <0x80140308 0x08>; 94 status = "disabled"; 95 #gpio-cells = <2>; 96 }; 97 98 gpioc: gpio@80140310 { 99 compatible = "telink,b91-gpio"; 100 gpio-controller; 101 interrupt-parent = <&plic0>; 102 interrupts = <25 1>, <26 1>, <27 1>; 103 reg = <0x80140310 0x08>; 104 status = "disabled"; 105 #gpio-cells = <2>; 106 }; 107 108 gpiod: gpio@80140318 { 109 compatible = "telink,b91-gpio"; 110 gpio-controller; 111 interrupt-parent = <&plic0>; 112 interrupts = <25 1>, <26 1>, <27 1>; 113 reg = <0x80140318 0x08>; 114 status = "disabled"; 115 #gpio-cells = <2>; 116 }; 117 118 gpioe: gpio@80140320 { 119 compatible = "telink,b91-gpio"; 120 gpio-controller; 121 interrupt-parent = <&plic0>; 122 interrupts = <25 1>, <26 1>, <27 1>; 123 reg = <0x80140320 0x08>; 124 status = "disabled"; 125 #gpio-cells = <2>; 126 }; 127 128 plic0: interrupt-controller@e4000000 { 129 compatible = "sifive,plic-1.0.0"; 130 #address-cells = <0>; 131 #interrupt-cells = <2>; 132 interrupt-controller; 133 interrupts-extended = <&hlic 11>; 134 interrupt-parent = <&cpu0>; 135 reg = <0xe4000000 0x00210000>; 136 riscv,max-priority = <3>; 137 riscv,ndev = <63>; 138 }; 139 140 uart0: serial@80140080 { 141 compatible = "telink,b91-uart"; 142 reg = <0x80140080 0x40>; 143 interrupts = <19 1>; 144 interrupt-parent = <&plic0>; 145 status = "disabled"; 146 }; 147 148 uart1: serial@801400C0 { 149 compatible = "telink,b91-uart"; 150 reg = <0x801400C0 0x40>; 151 interrupts = <18 1>; 152 interrupt-parent = <&plic0>; 153 status = "disabled"; 154 }; 155 156 ieee802154: ieee802154@80140800 { 157 compatible = "telink,b91-zb"; 158 reg = <0x80140800 0x800>; 159 interrupt-parent = <&plic0>; 160 interrupts = <15 2>; 161 status = "disabled"; 162 }; 163 164 trng0: trng@80101800 { 165 compatible = "telink,b91-trng"; 166 reg = <0x80101800 0x20>; 167 status = "disabled"; 168 }; 169 170 pwm0: pwm@80140400 { 171 compatible = "telink,b91-pwm"; 172 reg = <0x80140400 0x80>; 173 channels = <6>; 174 status = "disabled"; 175 #pwm-cells = <3>; 176 }; 177 178 hspi: spi@81FFFFC0 { 179 compatible = "telink,b91-spi"; 180 reg = <0x81FFFFC0 0x40>; 181 peripheral-id = "HSPI_MODULE"; 182 cs0-pin = "0"; 183 cs1-pin = "0"; 184 cs2-pin = "0"; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 status = "disabled"; 188 }; 189 190 pspi: spi@80140040 { 191 compatible = "telink,b91-spi"; 192 reg = <0x80140040 0x40>; 193 peripheral-id = "PSPI_MODULE"; 194 cs0-pin = "0"; 195 cs1-pin = "0"; 196 cs2-pin = "0"; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 status = "disabled"; 200 }; 201 202 i2c: i2c@80140280 { 203 compatible = "telink,b91-i2c"; 204 reg = <0x80140280 0x40>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 status = "disabled"; 208 clock-frequency = <I2C_BITRATE_STANDARD>; 209 }; 210 211 adc: adc@ea { 212 compatible = "telink,b91-adc"; 213 reg = <0xea 0x18>; 214 status = "disabled"; 215 #io-channel-cells = <1>; 216 }; 217 218 pinctrl: pinctrl@80140330 { 219 compatible = "telink,b91-pinctrl"; 220 reg = <0x80140330 0x28 221 0x80140306 0x28 222 0x0000000e 0x0C>; 223 reg-names = "pin_mux", 224 "gpio_en", 225 "pull_up_en"; 226 status = "okay"; 227 }; 228 }; 229}; 230
