1/*
2 * Copyright (C) 2021 StarFive, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "starfive_jh7100_clk.dtsi"
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	#address-cells = <2>;
12	#size-cells = <2>;
13	compatible = "sifive,freedom-u74-arty";
14	model = "sifive,freedom-u74-arty";
15
16	cpus: cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		compatible = "starfive,fu74-g000";
20		cpu@0 {
21			clock-frequency = <0>;
22			compatible = "starfive,rocket0", "riscv";
23			d-cache-block-size = <64>;
24			d-cache-sets = <64>;
25			d-cache-size = <32768>;
26			d-tlb-sets = <1>;
27			d-tlb-size = <32>;
28			device_type = "cpu";
29			i-cache-block-size = <64>;
30			i-cache-sets = <64>;
31			i-cache-size = <32768>;
32			i-tlb-sets = <1>;
33			i-tlb-size = <32>;
34			mmu-type = "riscv,sv39";
35			next-level-cache = <&cachectrl>;
36			reg = <0>;
37			riscv,isa = "rv64gc";
38			starfive,itim = <&itim0>;
39			status = "okay";
40			tlb-split;
41			cpu0intctrl: interrupt-controller {
42				compatible = "riscv,cpu-intc";
43				#address-cells = <0>;
44				#interrupt-cells = <1>;
45				interrupt-controller;
46			};
47		};
48
49		cpu@1 {
50			clock-frequency = <0>;
51			compatible = "starfive,rocket0", "riscv";
52			d-cache-block-size = <64>;
53			d-cache-sets = <64>;
54			d-cache-size = <32768>;
55			d-tlb-sets = <1>;
56			d-tlb-size = <32>;
57			device_type = "cpu";
58			i-cache-block-size = <64>;
59			i-cache-sets = <64>;
60			i-cache-size = <32768>;
61			i-tlb-sets = <1>;
62			i-tlb-size = <32>;
63			mmu-type = "riscv,sv39";
64			next-level-cache = <&cachectrl>;
65			reg = <1>;
66			riscv,isa = "rv64gc";
67			starfive,itim = <&itim1>;
68			status = "okay";
69			tlb-split;
70			cpu1intctrl: interrupt-controller {
71				compatible = "riscv,cpu-intc";
72				#address-cells = <0>;
73				#interrupt-cells = <1>;
74				interrupt-controller;
75			};
76		};
77	};
78
79	ram0:memory@80000000 {
80		device_type = "memory";
81		reg = <0x0 0x80000000 0x2 0x0>;
82	};
83
84	soc {
85		#address-cells = <2>;
86		#size-cells = <2>;
87		#clock-cells = <1>;
88		compatible = "starfive,freedom-u74-arty", "simple-bus";
89		ranges;
90
91		cachectrl: cache-controller@2010000 {
92			cache-block-size = <64>;
93			cache-level = <2>;
94			cache-sets = <2048>;
95			cache-size = <2097152>;
96			cache-unified;
97			compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
98			interrupt-parent = <&plic>;
99			interrupts = <128 1>, <131 1>, <129 1>, <130 1>;
100			/*next-level-cache = <&L40 &L36>;*/
101			reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
102			reg-names = "control", "sideband";
103		};
104
105		itim0: itim@1808000 {
106			compatible = "starfive,itim0";
107			reg = <0x0 0x1808000 0x0 0x8000>;
108			reg-names = "mem";
109		};
110
111		itim1: itim@1820000 {
112			compatible = "starfive,itim0";
113			reg = <0x0 0x1820000 0x0 0x8000>;
114			reg-names = "mem";
115		};
116
117		clint: clint@2000000 {
118			compatible = "starfive,jh7100-clint", "sifive,clint0";
119			interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
120					       &cpu1intctrl 3 &cpu1intctrl 7>;
121			reg = <0x0 0x2000000 0x0 0x10000>;
122		};
123
124		plic: plic@c000000 {
125			compatible = "sifive,plic-1.0.0";
126			#address-cells = <0>;
127			#interrupt-cells = <2>;
128			interrupt-controller;
129			interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9
130					       &cpu1intctrl 11 &cpu1intctrl 9 >;
131			reg = <0x0 0x0c000000 0x0 0x04000000>;
132			riscv,max-priority = <7>;
133			riscv,ndev = <127>;
134		};
135
136		uart3: serial@12440000 {
137			compatible = "ns16550", "snps,dw-apb-uart";
138			interrupt-parent = <&plic>;
139			interrupts = <73 1>;
140			reg = <0x0 0x12440000 0x0 0x10000>;
141			reg-shift = <2>;
142			clocks = <&uartclk>, <&apb2clk>;
143			clock-names = "baudclk", "apb_pclk";
144			clock-frequency = <100000000>;
145			current-speed = <115200>;
146			status = "disabled";
147		};
148
149		uart2: serial@12430000 {
150			compatible = "ns16550", "snps,dw-apb-uart";
151			interrupt-parent = <&plic>;
152			interrupts = <72 1>;
153			reg = <0x0 0x12430000 0x0 0x10000>;
154			reg-shift = <2>;
155			clocks = <&uartclk>, <&apb2clk>;
156			clock-names = "baudclk", "apb_pclk";
157			clock-frequency = <100000000>;
158			current-speed = <115200>;
159			status = "disabled";
160		};
161
162		uart1: hs_serial@11880000 {
163			compatible = "ns16550", "snps,dw-apb-uart";
164			interrupt-parent = <&plic>;
165			interrupts = <93 1>;
166			reg = <0x0 0x11880000 0x0 0x10000>;
167			reg-shift = <2>;
168			clocks = <&hs_uartclk>, <&apb1clk>;
169			clock-names = "baudclk","apb_pclk";
170			clock-frequency = <74250000>;
171			current-speed = <115200>;
172			status = "disabled";
173		};
174
175		uart0: hs_serial@11870000 {
176			compatible = "ns16550", "snps,dw-apb-uart";
177			interrupt-parent = <&plic>;
178			interrupts = <92 1>;
179			reg = <0x0 0x11870000 0x0 0x10000>;
180			reg-shift = <2>;
181			clocks = <&hs_uartclk>, <&apb1clk>;
182			clock-names = "baudclk", "apb_pclk";
183			clock-frequency = <74250000>;
184			current-speed = <115200>;
185			status = "disabled";
186		};
187	};
188};
189