1/*
2 * Copyright (c) 2023 Meta
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16		cpu@0 {
17			clock-frequency = <0>;
18			compatible = "renode,virt", "riscv";
19			device_type = "cpu";
20			reg = <0>;
21			riscv,isa = "rv32imac_zicsr_zifencei";
22			hlic: interrupt-controller {
23				compatible = "riscv,cpu-intc";
24				#address-cells = <0>;
25				#interrupt-cells = <1>;
26				interrupt-controller;
27			};
28		};
29	};
30
31	soc {
32		#address-cells = <1>;
33		#size-cells = <1>;
34		compatible = "renode,virt-soc", "simple-bus";
35		ranges;
36
37		flash0: flash@80000000 {
38			compatible = "soc-nv-flash";
39			reg = <0x80000000 DT_SIZE_M(4)>;
40		};
41
42		sram0: memory@80400000 {
43			compatible = "mmio-sram";
44			reg = <0x80400000 DT_SIZE_M(4)>;
45		};
46
47		clint: clint@2000000 {
48			compatible = "sifive,clint0";
49			interrupts-extended = <&hlic 3>, <&hlic 7>;
50			reg = <0x2000000 0x10000>;
51		};
52
53		plic0: interrupt-controller@c000000 {
54			compatible = "sifive,plic-1.0.0";
55			#address-cells = <0>;
56			#interrupt-cells = <2>;
57			interrupt-controller;
58			interrupts-extended = <&hlic 11>;
59			reg = <0xc000000 0x04000000>;
60			riscv,max-priority = <1>;
61			riscv,ndev = <1023>;
62		};
63
64		plic1: interrupt-controller@8000000 {
65			compatible = "sifive,plic-1.0.0";
66			#address-cells = <0>;
67			#interrupt-cells = <2>;
68			interrupt-controller;
69			interrupts-extended = <&hlic 4>;
70			reg = <0x8000000 0x04000000>;
71			riscv,max-priority = <1>;
72			riscv,ndev = <1023>;
73		};
74
75		uart0: uart@10000000 {
76			interrupts = < 0x0a 1 >;
77			interrupt-parent = < &plic0 >;
78			clock-frequency = <150000000>;
79			current-speed = <115200>;
80			reg = < 0x10000000 0x100 >;
81			compatible = "ns16550";
82			reg-shift = < 0 >;
83			status = "disabled";
84		};
85
86		uart1: uart@10000100 {
87			interrupts = < 0x0a 1 >;
88			interrupt-parent = < &plic1 >;
89			clock-frequency = <150000000>;
90			current-speed = <115200>;
91			reg = < 0x10000100 0x100 >;
92			compatible = "ns16550";
93			reg-shift = < 0 >;
94			status = "disabled";
95		};
96	};
97};
98