1description: INFINEON XMC4XXX UART
2
3compatible: "infineon,xmc4xxx-uart"
4
5include: [uart-controller.yaml, pinctrl-device.yaml]
6
7properties:
8  reg:
9    required: true
10
11  input-src:
12    description: |
13      Connects the UART receive line (USIC DX0 input) to a specific GPIO pin.
14      The USIC DX0 input is a multiplexer which connects to different GPIO pins.
15      Refer to the XMC4XXX reference manual for the GPIO pin/mux mappings. DX0G
16      is the loopback input line.
17    type: string
18    required: true
19    enum:
20      - "DX0A"
21      - "DX0B"
22      - "DX0C"
23      - "DX0D"
24      - "DX0E"
25      - "DX0F"
26      - "DX0G"
27
28  pinctrl-0:
29    required: true
30
31  pinctrl-names:
32    required: true
33
34  fifo-start-offset:
35    description: |
36      Each USIC0..2 has a fifo that is shared between two channels. For example,
37      usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset
38      where the tx and rx fifos will start. When sharing the fifo, the user must properly
39      define the offset based on the configuration of the other channel. The fifo has a
40      capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned
41      boundaries.
42
43    required: true
44    type: int
45
46  fifo-tx-size:
47    description: |
48      Fifo size used for buffering transmit bytes. A value of 0 implies that
49      the fifo is not used while transmitting. transmitting. If the UART is used in async mode
50      then fifo-tx-size should be set to 0.
51    required: true
52    type: int
53    enum:
54      - 0
55      - 2
56      - 4
57      - 8
58      - 16
59      - 32
60      - 64
61
62  fifo-rx-size:
63    description: |
64      Fifo size used for buffering received bytes. A value of 0 implies that
65      the fifo is not used while receiving. If the UART is used in async mode
66      then fifo-rx-size should be set to 0.
67    required: true
68    type: int
69    enum:
70      - 0
71      - 2
72      - 4
73      - 8
74      - 16
75      - 32
76      - 64
77
78  interrupts:
79    description: |
80      IRQ number and priority to use for interrupt driven UART.
81      USIC0..2 have their own interrupt range as follows:
82      USIC0 = [84, 89]
83      USIC1 = [90, 95]
84      USIC2 = [96, 101]
85
86  dmas:
87    description: |
88      Optional TX & RX dma specifiers used by async UART.
89
90      The dmas are referenced in the UART node using the following syntax:
91      dmas = <&dma1 1 0 XMC4XXX_SET_CONFIG(10,6)>, <&dma1 2 0 XMC4XXX_SET_CONFIG(11,6)>;
92      where the first entry is for the TX, and the second for RX.
93
94      The parameters in the dma entry are: dma device phandle, dma channel, dma priority (0 is
95      lowest and 7 is highest), and an opaque entry for the dma line routing parameters set
96      by the macro XMC4XXX_SET_CONFIG(line, request_source). Use the following steps to properly
97      select parameters line, request_source:
98      1. Select a dma device and a free dma channel.
99      1. Select a free dma line. dma0 device can only connect to lines [0, 7] and
100         dma1 can connect to lines [8, 11].
101      2. For a given interrupt, calculate the service request (SR) number. Note the following
102         simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
103         In USIC1, interrupt 90->SR0, 91->SR1, etc.
104      3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
105         manual.
106
107      For example, say we select interrupt 85 on USIC0, dma0, channel 3, priority 4, and line 7.
108      The interrupt would map to SR1. From Table "DMA Request Source Selection", request_source
109      would need to be set to 10 and the dts entry would be:
110      dma = <&dma0 3 4 XMC4XXX_SET_CONFIG(7,10) ... >;
111
112  dma-names:
113    description: |
114      Required if the dmas property exists. Should be set to "tx" and "rx"
115      to match the dmas property.
116
117      For example
118         dma-names = "tx", "rx";
119