1# Copyright (c) 2020, Linaro limited
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    STM32 QSPI device representation. A stm32 quadspi node would typically
6    looks to this:
7
8        &quadspi {
9            pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
10                         &quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
11                         &quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
12
13            dmas = <&dma1 5 5 0x0000 0x03>;
14            dma-names = "tx_rx";
15
16            status = "okay";
17        };
18
19compatible: "st,stm32-qspi"
20
21include: [base.yaml, pinctrl-device.yaml]
22
23bus: qspi
24
25properties:
26  reg:
27    required: true
28
29  interrupts:
30    required: true
31
32  pinctrl-0:
33    required: true
34
35  pinctrl-names:
36    required: true
37
38  dmas:
39    description: |
40      Optional DMA channel specifier. If DMA should be used, specifier should
41      hold a phandle reference to the dma controller (not the DMAMUX even if present),
42      the channel number, the slot number, channel configuration and finally features.
43      (depending on the type of DMA: 'features' is optional)
44
45      When a DMAMUX is present and enabled, the channel is the dma one
46      (not dmamux channel). The request is given by the DMAMUX (no 'features' required).
47
48      For example with DMA 2 for TX/RX on QSPI like stm32l496 (no 'features')
49         /* select DMA2 channel 7 request 3 for QUADSPI */
50         dmas = <&dma2 7 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>;
51      For example with a DMAMUX for TX/RX on QSPI like stm32wb55  (no 'features')
52         /* select DMA2 channel 0, request 20 for QUADSPI */
53         dmas = <&dma2 0 20 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>;
54
55  dma-names:
56    description: |
57      DMA channel name. If DMA should be used, expected value is "tx_rx".
58
59      For example
60         dma-names = "tx_rx";
61
62  dual-flash:
63    type: boolean
64    description: |
65      configuration to enable the dual flash mode of the QSPI peripheral
66      where two external quad SPI Flash memories (FLASH 1 and FLASH 2) are used
67      in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle,
68      effectively doubling the throughput as well as the capacity.
69      When true, the Flash ID number <flash-id> is useless.
70
71  flash-id:
72    type: int
73    description: |
74      Flash ID number. This number, if defined, helps to select the right
75      QSPI GPIO banks (defined as 'quadspi_bk[1/2]' in pinctrl property)
76      to communicate with flash memory.
77      Valid only if the <dual-flash> is not set.
78
79      For example
80         flash-id = <2>;
81