1# Copyright (c) 2022 Antmicro <www.antmicro.com>
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  SiFive FE310 IO Function (iof) binding covers the IOF_EN/IOF_SEL registers
6  that are a subset of the GPIO controller. You can use this node to set the
7  value of IOF_EN/IOF_SEL registers to control pin settings.
8
9  Device pin configuration should be placed in the child nodes of this node.
10  Populate the 'pinmux' field with a pair consisting of a pin number and its IO
11  function. The available IO functions are:
12    - SIFIVE_PINMUX_IOF0
13    - SIFIVE_PINMUX_IOF1
14
15  For example, setting pins 16 and 17 both to IOF0 would look like this:
16
17    #include <dt-bindings/pinctrl/sifive-pinctrl.h>
18
19    &pinctrl {
20      uart0_rx_default: uart0_rx_default {
21        pinmux = <16 SIFIVE_PINMUX_IOF0>;
22      };
23      uart0_tx_default: uart0_tx_default {
24        pinmux = <17 SIFIVE_PINMUX_IOF0>;
25      };
26    };
27
28compatible: "sifive,pinctrl"
29
30include: base.yaml
31
32properties:
33  reg:
34    required: true
35
36child-binding:
37  description: |
38    This binding gives a base representation of the SiFive FE310 pins
39    configuration.
40
41  properties:
42    pinmux:
43      required: true
44      type: array
45      description: |
46        SiFive FE310 pin's configuration (pin, IO function).
47