1# Copyright (c) 2021, STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    STM32 OSPI Flash controller supporting the JEDEC CFI interface
6
7    Representation of a serial flash on a octospi bus:
8
9        mx25lm51245: ospi-nor-flash@70000000 {
10                compatible = "st,stm32-ospi-nor";
11                reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
12                data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
13                data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
14                ospi-max-frequency = <DT_FREQ_M(50)>;
15                status = "okay";
16        };
17
18compatible: "st,stm32-ospi-nor"
19
20include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
21
22on-bus: ospi
23
24properties:
25  reg:
26    required: true
27    description: Flash Memory base address and size in bytes
28  ospi-max-frequency:
29    type: int
30    required: true
31    description: Maximum clock frequency of device's OSPI interface in Hz
32  reset-gpios:
33    type: phandle-array
34    description: RESETn pin
35  reset-gpios-duration:
36    type: int
37    description: The duration (in ms) for the flash memory reset pulse
38  spi-bus-width:
39    type: int
40    required: true
41    description: |
42     The width of (Octo)SPI bus to which flash memory is connected.
43
44     Possible values are :
45      - OSPI_SPI_MODE  <1> = SPI mode on 1 data line
46      - OSPI_DUAL_MODE <2> = Dual mode on 2 data lines
47      - OSPI_QUAD_MODE <4> = Quad mode on 4 data lines
48      - OSPI_OPI_MODE  <8> = Octo mode on 8 data lines
49    enum:
50      - 1
51      - 2
52      - 4
53      - 8
54  data-rate:
55    type: int
56    required: true
57    description: |
58     The SPI data Rate is STR or DTR
59
60     Possible values are :
61      - OSPI_STR_TRANSFER <1> = Single Rate Transfer
62      - OSPI_DTR_TRANSFER <2> = Dual Rate Transfer (only with OSPI_OPI_MODE)
63    enum:
64      - 1
65      - 2
66  writeoc:
67    type: string
68    enum:
69      - "PP"            # Page program, PP (0x02) up to 256 bytes
70      - "PP_1_1_2"      # Dual page program, PP 1-1-2 (0xA2)
71      - "PP_1_1_4"      # Quad data line SPI, PP 1-1-4 (0x32)
72      - "PP_1_4_4"      # Quad data line SPI, PP 1-4-4 (0x38)
73    description: |
74      The value encodes number of I/O lines used for the opcode,
75      address, and data.
76
77      There is no info about quad page program opcodes in the SFDP
78      tables, hence it has been assumed that NOR flash memory
79      supporting 1-4-4 mode also would support fast page programming.
80
81      Intended for modes other than OSPI_OPI_MODE.
82
83      If absent, then program page opcode is determined by the
84      `spi-bus-width`:
85
86      * OSPI_SPI_MODE -> PP 1-1-1 (0x02)
87      * OSPI_DUAL_MODE -> PP 1-1-2 (0xA2)
88      * OSPI_QUAD_MODE -> PP 1-4-4 (0x38)
89  four-byte-opcodes:
90    type: boolean
91    description: |
92      Some NOR-Flash ICs use different opcodes when operating in
93      4 byte addressing mode.
94
95      When enabled, then 3 byte opcodes will be converted to
96      4 byte opcodes.
97
98      * PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12)
99      * PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34)
100      * PP 1-4-4 (0x38) -> PP 1-4-4 4B (0x3E)
101
102      * READ 1-1-1 (0x03) -> READ 1-1-1 4B (0x13)
103      * READ FAST 1-1-1 (0x0B) -> READ FAST 1-1-1 4B (0x0C)
104      * DREAD 1-1-2 (0x3B) -> DREAD 1-1-2 4B (0x3C)
105      * 2READ 1-2-2 (0xBB) -> 2READ 1-2-2 4B (0xBC)
106      * QREAD 1-1-4 (0x6B) -> QREAD 1-1-4 4B (0x6C)
107      * 4READ 1-4-4 (0xEB) -> 4READ 1-4-4 4B (0xEC)
108