1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
6
7  Takes one of clk_hse, pll2 or clk_hsi as input clock.
8  When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
9  pll2, configurable prescaler is used.
10
11  Output clock frequency can be computed with the following formula:
12
13    f(PLLCLK) = f(PLLIN) x PLLMUL         --> SYSCLK (System Clock)
14
15    with, depending on the case:
16            f(PLLIN) = f(input_clk) / 2       if input_clk = clk_hsi
17            f(PLLIN) = f(input_clk) / PREDIV  if input_clk = clk_hse or pll2
18
19  The PLL output frequency must not exceed 72 MHz.
20
21
22compatible: "st,stm32f105-pll-clock"
23
24include: [clock-controller.yaml, base.yaml]
25
26properties:
27  "#clock-cells":
28    const: 0
29
30  clocks:
31    required: true
32
33  mul:
34    type: int
35    required: true
36    description: |
37        Main PLL multiplication factor for VCO.
38        Note: For x6.5 multiplier value, please use "mul = <15>;"
39    enum:
40      - 4   # x4
41      - 5   # x5
42      - 6   # x6
43      - 7   # x7
44      - 8   # x8
45      - 9   # x9
46      - 15  # x6.5
47
48  prediv:
49    type: int
50    required: true
51    description: |
52        Configurable prescaler
53        Valid range: 1 - 16
54
55  otgfspre:
56    type: boolean
57    description: |
58        Optional PLL output divisor to generate a 48MHz USB clock.
59        When set, PLL output clock is not divided.
60        Otherwise, PLL output clock is divided by 1.5.
61