1# Copyright (c) 2022 BrainCo Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: GigaDevice GD32 ADC
5
6# gd32 adc irq have some special cases as below:
7#   1. adc number no larger than 3.
8#   2. adc0 and adc1 share the same irq number.
9#   3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
10#
11# To cover this cases, adc_gd32 driver use node-label 'adc0', 'adc1' and
12# 'adc2' to handle gd32 adc irq config directly.
13#
14# Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
15# 'adc1' and 'adc2'.
16
17compatible: "gd,gd32-adc"
18
19include: [adc-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
20
21properties:
22  reg:
23    required: true
24
25  resets:
26    required: true
27
28  clocks:
29    required: true
30
31  rcu-clock-source:
32    type: int
33    description: |
34      Some GD32 ADC have additional clock source, like IRC14M or IRC28M.
35      This property used to select the clock and related prescaler, valid
36      values defined at 'dts-bindings/adc/gd32xxx.h' headers.
37
38  channels:
39    type: int
40    description: Number of external channels
41    required: true
42
43  interrupts:
44    required: true
45
46  "#io-channel-cells":
47    const: 1
48
49  pinctrl-0:
50    required: true
51
52  pinctrl-names:
53    required: true
54
55io-channel-cells:
56  - input
57