1/*
2 * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/*
8 * Derived from DTS extracted with:
9 *
10 *   qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
11 *         -machine dumpdtb=virt.dtb
12 *
13 *   dtc -I dtb -O dts virt.dtb
14 */
15
16#include <mem.h>
17#include <arm64/armv8-a.dtsi>
18#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19#include <zephyr/dt-bindings/pcie/pcie.h>
20
21/ {
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a53";
32			reg = <0>;
33		};
34
35		cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			reg = <1>;
39		};
40	};
41
42	timer {
43		compatible = "arm,armv8-timer";
44		interrupt-parent = <&gic>;
45		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
46			      IRQ_DEFAULT_PRIORITY>,
47			     <GIC_PPI 14 IRQ_TYPE_LEVEL
48			      IRQ_DEFAULT_PRIORITY>,
49			     <GIC_PPI 11 IRQ_TYPE_LEVEL
50			      IRQ_DEFAULT_PRIORITY>,
51			     <GIC_PPI 10 IRQ_TYPE_LEVEL
52			      IRQ_DEFAULT_PRIORITY>;
53	};
54
55	uartclk: apb-pclk {
56		compatible = "fixed-clock";
57		clock-frequency = <24000000>;
58		#clock-cells = <0>;
59	};
60
61	soc {
62		#address-cells = <2>;
63		#size-cells = <2>;
64		ranges;
65
66		interrupt-parent = <&gic>;
67
68		gic: interrupt-controller@8000000 {
69			compatible = "arm,gic-v3", "arm,gic";
70			reg = <0x00 0x8000000 0x00 0x010000>,
71			      <0x00 0x80a0000 0x00 0xf60000>;
72			interrupt-controller;
73			#interrupt-cells = <4>;
74			status = "okay";
75			#size-cells = <0x02>;
76			#address-cells = <0x02>;
77
78			its: its@8080000 {
79				compatible = "arm,gic-v3-its";
80				reg = <0x00 0x8080000 0x00 0x20000>;
81				msi-controller;
82			};
83		};
84
85		uart0: uart@9000000 {
86			compatible = "arm,pl011";
87			reg = <0x00 0x9000000 0x00 0x1000>;
88			status = "disabled";
89			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL 0>;
90			interrupt-names = "irq_0";
91			clocks = <&uartclk>;
92		};
93
94		flash0: flash@0 {
95			compatible = "cfi-flash";
96			bank-width = <4>;
97			/* As this is pointed to by zephyr,flash we can only handle
98			 * one value in the reg property, so we comment out the
99			 * second flash bank for now
100			 */
101			reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */>;
102		};
103
104		pcie: pcie@4010000000 {
105			compatible = "pci-host-ecam-generic";
106			device_type = "pci";
107			reg = <0x40 0x10000000 0x00 0x10000000>;
108			#size-cells = <0x02>;
109			#address-cells = <0x03>;
110			ranges = <0x1000000 0x00 0x00        0x00 0x3eff0000  0x00 0x10000
111				  0x2000000 0x00 0x10000000  0x00 0x10000000  0x00 0x2eff0000
112				  0x3000000 0x80 0x00        0x80 0x00        0x80 0x00>;
113			#interrupt-cells = <0x01>;
114			interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
115			interrupt-map = <0x00   0x00 0x00 1 &gic 0 0 GIC_SPI
116					 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
117					 0x00   0x00 0x00 2 &gic 0 0 GIC_SPI
118					 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
119					 0x00   0x00 0x00 3 &gic 0 0 GIC_SPI
120					 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
121					 0x00   0x00 0x00 4 &gic 0 0 GIC_SPI
122					 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
123
124					 0x800  0x00 0x00 1 &gic 0 0 GIC_SPI
125					 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
126					 0x800  0x00 0x00 2 &gic 0 0 GIC_SPI
127					 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
128					 0x800  0x00 0x00 3 &gic 0 0 GIC_SPI
129					 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
130					 0x800  0x00 0x00 4 &gic 0 0 GIC_SPI
131					 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
132
133					 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI
134					 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
135					 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI
136					 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
137					 0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI
138					 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
139					 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI
140					 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
141
142					 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI
143					 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
144					 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI
145					 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
146					 0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI
147					 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
148					 0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI
149					 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
150			msi-parent = <&its>;
151			bus-range = <0x00 0xff>;
152		};
153	};
154};
155