1/* 2 * Copyright 2022,2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <freq.h> 9#include <arm64/armv8-a.dtsi> 10#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/i2c/i2c.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a55"; 27 reg = <0>; 28 }; 29 30 cpu@100 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a55"; 33 reg = <0x100>; 34 }; 35 36 }; 37 38 arch_timer: timer { 39 compatible = "arm,armv8-timer"; 40 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL 41 IRQ_DEFAULT_PRIORITY>, 42 <GIC_PPI 14 IRQ_TYPE_LEVEL 43 IRQ_DEFAULT_PRIORITY>, 44 <GIC_PPI 11 IRQ_TYPE_LEVEL 45 IRQ_DEFAULT_PRIORITY>, 46 <GIC_PPI 10 IRQ_TYPE_LEVEL 47 IRQ_DEFAULT_PRIORITY>; 48 interrupt-parent = <&gic>; 49 }; 50 51 gic: interrupt-controller@48000000 { 52 compatible = "arm,gic-v3", "arm,gic"; 53 reg = <0x48000000 0x10000>, /* GIC Dist */ 54 <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ 55 interrupt-controller; 56 #interrupt-cells = <4>; 57 status = "okay"; 58 }; 59 60 iomuxc: iomuxc@443c0000 { 61 compatible = "nxp,imx-iomuxc"; 62 reg = <0x443c0000 DT_SIZE_K(64)>; 63 status = "okay"; 64 pinctrl: pinctrl { 65 status = "okay"; 66 compatible = "nxp,imx93-pinctrl"; 67 }; 68 }; 69 70 ana_pll: ana_pll@44480000 { 71 compatible = "nxp,imx-ana"; 72 reg = <0x44480000 DT_SIZE_K(64)>; 73 }; 74 75 ccm: ccm@44450000 { 76 compatible = "nxp,imx-ccm-rev2"; 77 reg = <0x44450000 DT_SIZE_K(64)>; 78 #clock-cells = <3>; 79 }; 80 81 gpio1: gpio@47400000 { 82 compatible = "nxp,imx-rgpio"; 83 reg = <0x47400000 DT_SIZE_K(64)>; 84 interrupt-parent = <&gic>; 85 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 86 <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 87 gpio-controller; 88 #gpio-cells = <2>; 89 }; 90 91 gpio2: gpio@43810000 { 92 compatible = "nxp,imx-rgpio"; 93 reg = <0x43810000 DT_SIZE_K(64)>; 94 interrupt-parent = <&gic>; 95 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 96 <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 97 gpio-controller; 98 #gpio-cells = <2>; 99 }; 100 101 gpio3: gpio@43820000 { 102 compatible = "nxp,imx-rgpio"; 103 reg = <0x43820000 DT_SIZE_K(64)>; 104 interrupt-parent = <&gic>; 105 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 106 <GIC_SPI 60 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 107 gpio-controller; 108 #gpio-cells = <2>; 109 }; 110 111 gpio4: gpio@43830000 { 112 compatible = "nxp,imx-rgpio"; 113 reg = <0x43830000 DT_SIZE_K(64)>; 114 interrupt-parent = <&gic>; 115 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 116 <GIC_SPI 190 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 117 gpio-controller; 118 #gpio-cells = <2>; 119 }; 120 121 lpuart1: serial@44380000 { 122 compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart"; 123 reg = <0x44380000 DT_SIZE_K(64)>; 124 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 125 interrupt-names = "irq_0"; 126 interrupt-parent = <&gic>; 127 clocks = <&ccm IMX_CCM_LPUART1_CLK 0x6c 24>; 128 status = "disabled"; 129 }; 130 131 lpuart2: serial@44390000 { 132 compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart"; 133 reg = <0x44390000 DT_SIZE_K(64)>; 134 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 135 interrupt-names = "irq_0"; 136 interrupt-parent = <&gic>; 137 clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>; 138 status = "disabled"; 139 }; 140 141 lpi2c1: i2c@44340000 { 142 compatible = "nxp,imx-lpi2c"; 143 clock-frequency = <I2C_BITRATE_STANDARD>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 reg = <0x44340000 0x4000>; 147 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 148 interrupt-parent = <&gic>; 149 clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>; 150 status = "disabled"; 151 }; 152 153 lpi2c2: i2c@44350000 { 154 compatible = "nxp,imx-lpi2c"; 155 clock-frequency = <I2C_BITRATE_STANDARD>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 reg = <0x44350000 0x4000>; 159 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 160 interrupt-parent = <&gic>; 161 clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>; 162 status = "disabled"; 163 }; 164 165 lpi2c3: i2c@42530000 { 166 compatible = "nxp,imx-lpi2c"; 167 clock-frequency = <I2C_BITRATE_STANDARD>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 reg = <0x42530000 0x4000>; 171 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 172 interrupt-parent = <&gic>; 173 clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>; 174 status = "disabled"; 175 }; 176 177 lpi2c4: i2c@42540000 { 178 compatible = "nxp,imx-lpi2c"; 179 clock-frequency = <I2C_BITRATE_STANDARD>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 reg = <0x42540000 0x4000>; 183 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 184 interrupt-parent = <&gic>; 185 clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>; 186 status = "disabled"; 187 }; 188 189 lpi2c5: i2c@426b0000 { 190 compatible = "nxp,imx-lpi2c"; 191 clock-frequency = <I2C_BITRATE_STANDARD>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 reg = <0x426b0000 0x4000>; 195 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 196 interrupt-parent = <&gic>; 197 clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>; 198 status = "disabled"; 199 }; 200 201 lpi2c6: i2c@426c0000 { 202 compatible = "nxp,imx-lpi2c"; 203 clock-frequency = <I2C_BITRATE_STANDARD>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 reg = <0x426c0000 0x4000>; 207 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 208 interrupt-parent = <&gic>; 209 clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>; 210 status = "disabled"; 211 }; 212 213 lpi2c7: i2c@426d0000 { 214 compatible = "nxp,imx-lpi2c"; 215 clock-frequency = <I2C_BITRATE_STANDARD>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 reg = <0x426d0000 0x4000>; 219 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 220 interrupt-parent = <&gic>; 221 clocks = <&ccm IMX_CCM_LPI2C7_CLK 0x80 24>; 222 status = "disabled"; 223 }; 224 225 lpi2c8: i2c@426e0000 { 226 compatible = "nxp,imx-lpi2c"; 227 clock-frequency = <I2C_BITRATE_STANDARD>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 reg = <0x426e0000 0x4000>; 231 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 232 interrupt-parent = <&gic>; 233 clocks = <&ccm IMX_CCM_LPI2C8_CLK 0x80 24>; 234 status = "disabled"; 235 }; 236 237 lpspi1: spi@44360000 { 238 compatible = "nxp,imx-lpspi"; 239 reg = <0x44360000 0x4000>; 240 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 241 interrupt-parent = <&gic>; 242 status = "disabled"; 243 clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 }; 247 248 lpspi2: spi@44370000 { 249 compatible = "nxp,imx-lpspi"; 250 reg = <0x44370000 0x4000>; 251 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 252 interrupt-parent = <&gic>; 253 status = "disabled"; 254 clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 lpspi3: spi@42550000 { 260 compatible = "nxp,imx-lpspi"; 261 reg = <0x42550000 0x4000>; 262 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 263 interrupt-parent = <&gic>; 264 status = "disabled"; 265 clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 }; 269 270 lpspi4: spi@42560000 { 271 compatible = "nxp,imx-lpspi"; 272 reg = <0x42560000 0x4000>; 273 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 274 interrupt-parent = <&gic>; 275 status = "disabled"; 276 clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 281 lpspi5: spi@426f0000 { 282 compatible = "nxp,imx-lpspi"; 283 reg = <0x426f0000 0x4000>; 284 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 285 interrupt-parent = <&gic>; 286 status = "disabled"; 287 clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 }; 291 292 lpspi6: spi@42700000 { 293 compatible = "nxp,imx-lpspi"; 294 reg = <0x42700000 0x4000>; 295 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 296 interrupt-parent = <&gic>; 297 status = "disabled"; 298 clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 }; 302 303 lpspi7: spi@42710000 { 304 compatible = "nxp,imx-lpspi"; 305 reg = <0x42710000 0x4000>; 306 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 307 interrupt-parent = <&gic>; 308 status = "disabled"; 309 clocks = <&ccm IMX_CCM_LPSPI7_CLK 0x6c 0>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 }; 313 314 lpspi8: spi@42720000 { 315 compatible = "nxp,imx-lpspi"; 316 reg = <0x42720000 0x4000>; 317 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 318 interrupt-parent = <&gic>; 319 status = "disabled"; 320 clocks = <&ccm IMX_CCM_LPSPI8_CLK 0x6c 2>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 }; 324 325 edma4: dma@42000000 { 326 compatible = "nxp,edma"; 327 reg = <0x42000000 (DT_SIZE_K(64) * 32)>; 328 valid-channels = <0>, <1>; 329 interrupt-parent = <&gic>; 330 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 331 <GIC_SPI 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 332 #dma-cells = <2>; 333 hal-cfg-index = <1>; 334 status = "disabled"; 335 }; 336 337 sai3: dai@42660000 { 338 compatible = "nxp,dai-sai"; 339 reg = <0x42660000 DT_SIZE_K(64)>; 340 mclk-is-output; 341 clocks = <&ccm IMX_CCM_SAI3_CLK 0x0 0x0>; 342 clock-names = "mclk1"; 343 interrupt-parent = <&gic>; 344 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 345 dai-index = <3>; 346 dmas = <&edma4 0 60>, <&edma4 1 61>; 347 dma-names = "tx", "rx"; 348 status = "disabled"; 349 }; 350 351 enet: enet@42890000 { 352 compatible = "nxp,enet1g"; 353 reg = <0x42890000 DT_SIZE_K(64)>; 354 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>; 355 status = "disabled"; 356 357 enet_mac: ethernet { 358 compatible = "nxp,enet-mac"; 359 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 360 interrupt-names = "COMMON"; 361 interrupt-parent = <&gic>; 362 nxp,mdio = <&enet_mdio>; 363 nxp,ptp-clock = <&enet_ptp_clock>; 364 status = "disabled"; 365 }; 366 enet_mdio: mdio { 367 compatible = "nxp,enet-mdio"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 status = "disabled"; 371 }; 372 enet_ptp_clock: ptp_clock { 373 compatible = "nxp,enet-ptp-clock"; 374 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 375 interrupt-parent = <&gic>; 376 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>; 377 status = "disabled"; 378 }; 379 }; 380 381 tpm1: tpm@44310000 { 382 compatible = "nxp,tpm-timer"; 383 reg = <0x44310000 DT_SIZE_K(64)>; 384 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 385 interrupt-names = "irq_0"; 386 interrupt-parent = <&gic>; 387 clocks = <&ccm IMX_CCM_TPM1_CLK 0 0>; 388 prescaler = <1>; 389 status = "disabled"; 390 }; 391 392 tpm2: tpm@44320000 { 393 compatible = "nxp,tpm-timer"; 394 reg = <0x44320000 DT_SIZE_K(64)>; 395 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 396 interrupt-names = "irq_0"; 397 interrupt-parent = <&gic>; 398 clocks = <&ccm IMX_CCM_TPM2_CLK 0 0>; 399 prescaler = <1>; 400 status = "disabled"; 401 }; 402 403 tpm3: tpm@424e0000 { 404 compatible = "nxp,tpm-timer"; 405 reg = <0x424e0000 DT_SIZE_K(64)>; 406 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 407 interrupt-names = "irq_0"; 408 interrupt-parent = <&gic>; 409 clocks = <&ccm IMX_CCM_TPM3_CLK 0 0>; 410 prescaler = <1>; 411 status = "disabled"; 412 }; 413 414 tpm4: tpm@424f0000 { 415 compatible = "nxp,tpm-timer"; 416 reg = <0x424f0000 DT_SIZE_K(64)>; 417 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 418 interrupt-names = "irq_0"; 419 interrupt-parent = <&gic>; 420 clocks = <&ccm IMX_CCM_TPM4_CLK 0 0>; 421 prescaler = <1>; 422 status = "disabled"; 423 }; 424 425 tpm5: tpm@42500000 { 426 compatible = "nxp,tpm-timer"; 427 reg = <0x42500000 DT_SIZE_K(64)>; 428 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 429 interrupt-names = "irq_0"; 430 interrupt-parent = <&gic>; 431 clocks = <&ccm IMX_CCM_TPM5_CLK 0 0>; 432 prescaler = <1>; 433 status = "disabled"; 434 }; 435 436 tpm6: tpm@42510000 { 437 compatible = "nxp,tpm-timer"; 438 reg = <0x42510000 DT_SIZE_K(64)>; 439 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 440 interrupt-names = "irq_0"; 441 interrupt-parent = <&gic>; 442 clocks = <&ccm IMX_CCM_TPM6_CLK 0 0>; 443 prescaler = <1>; 444 status = "disabled"; 445 }; 446 447}; 448 449&gpio1{ 450 pinmux = <&iomuxc1_i2c1_scl_gpio_io_gpio1_io00>, 451 <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>, 452 <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>, 453 <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>, 454 <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>, 455 <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>, 456 <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>, 457 <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>, 458 <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>, 459 <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>, 460 <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, 461 <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, 462 <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, 463 <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, 464 <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, 465 <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; 466}; 467 468&gpio2{ 469 pinmux = <&iomuxc1_gpio_io00_gpio_io_gpio2_io00>, 470 <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>, 471 <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>, 472 <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>, 473 <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>, 474 <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>, 475 <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>, 476 <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>, 477 <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>, 478 <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>, 479 <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, 480 <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, 481 <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, 482 <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, 483 <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, 484 <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, 485 <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, 486 <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, 487 <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, 488 <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, 489 <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, 490 <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, 491 <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, 492 <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, 493 <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, 494 <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, 495 <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, 496 <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, 497 <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, 498 <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; 499}; 500 501&gpio3{ 502 pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, 503 <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>, 504 <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>, 505 <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>, 506 <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>, 507 <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>, 508 <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>, 509 <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>, 510 <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>, 511 <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>, 512 <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, 513 <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, 514 <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, 515 <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, 516 <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, 517 <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, 518 <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, 519 <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, 520 <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, 521 <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, 522 <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, 523 <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, 524 <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, 525 <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, 526 <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, 527 <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, 528 <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, 529 <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, 530 <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, 531 <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, 532 <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, 533 <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; 534}; 535 536&gpio4{ 537 pinmux = <&iomuxc1_enet1_mdc_gpio_io_gpio4_io00>, 538 <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>, 539 <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>, 540 <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>, 541 <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>, 542 <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>, 543 <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>, 544 <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>, 545 <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>, 546 <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>, 547 <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, 548 <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, 549 <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, 550 <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, 551 <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, 552 <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, 553 <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, 554 <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, 555 <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, 556 <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, 557 <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, 558 <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, 559 <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, 560 <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, 561 <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, 562 <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, 563 <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, 564 <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, 565 <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, 566 <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; 567}; 568
