1/* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/pwm/pwm.h> 12#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 13#include <zephyr/dt-bindings/reset/stm32h7rs_reset.h> 14#include <zephyr/dt-bindings/adc/stm32h7_adc.h> 15#include <zephyr/dt-bindings/adc/adc.h> 16#include <zephyr/dt-bindings/memory-attr/memory-attr.h> 17#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 18#include <freq.h> 19 20/* 21 * STM32H7RS line contains has many common peripherals with STM32H7. 22 */ 23 24/ { 25 chosen { 26 zephyr,entropy = &rng; 27 zephyr,flash-controller = &flash; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-m7"; 37 reg = <0>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 41 mpu: mpu@e000ed90 { 42 compatible = "arm,armv7m-mpu"; 43 reg = <0xe000ed90 0x40>; 44 }; 45 }; 46 }; 47 48 /* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */ 49 sram0: memory@24000000 { 50 compatible = "mmio-sram"; 51 reg = <0x24000000 DT_SIZE_K(128)>; 52 }; 53 54 /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ 55 sram1: memory@30000000 { 56 reg = <0x30000000 DT_SIZE_K(16)>; 57 compatible = "zephyr,memory-region", "mmio-sram"; 58 zephyr,memory-region = "SRAM1"; 59 }; 60 61 /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ 62 sram2: memory@30004000 { 63 compatible = "zephyr,memory-region", "mmio-sram"; 64 reg = <0x30004000 DT_SIZE_K(16)>; 65 zephyr,memory-region = "SRAM2"; 66 }; 67 68 dtcm: memory@20000000 { 69 compatible = "zephyr,memory-region", "arm,dtcm"; 70 reg = <0x20000000 DT_SIZE_K(128)>; 71 zephyr,memory-region = "DTCM"; 72 }; 73 74 itcm: memory@0 { 75 compatible = "zephyr,memory-region", "arm,itcm"; 76 reg = <0x00000000 DT_SIZE_K(64)>; 77 zephyr,memory-region = "ITCM"; 78 }; 79 80 ext_memory: memory@70000000 { 81 compatible = "zephyr,memory-region"; 82 reg = <0x70000000 DT_SIZE_M(256)>; 83 zephyr,memory-region = "EXTMEM"; 84 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; 85 }; 86 87 clocks { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 clk_hse: clk-hse { 92 #clock-cells = <0>; 93 compatible = "st,stm32-hse-clock"; 94 status = "disabled"; 95 }; 96 97 clk_hsi: clk-hsi { 98 #clock-cells = <0>; 99 compatible = "st,stm32h7-hsi-clock"; 100 clock-frequency = <DT_FREQ_M(64)>; 101 status = "disabled"; 102 }; 103 104 clk_hsi48: clk-hsi48 { 105 #clock-cells = <0>; 106 compatible = "fixed-clock"; 107 clock-frequency = <DT_FREQ_M(48)>; 108 status = "disabled"; 109 }; 110 111 clk_csi: clk-csi { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <DT_FREQ_M(4)>; 115 status = "disabled"; 116 }; 117 118 clk_lse: clk-lse { 119 #clock-cells = <0>; 120 compatible = "st,stm32-lse-clock"; 121 clock-frequency = <32768>; 122 driving-capability = <0>; 123 status = "disabled"; 124 }; 125 126 clk_lsi: clk-lsi { 127 #clock-cells = <0>; 128 compatible = "fixed-clock"; 129 clock-frequency = <DT_FREQ_K(32)>; 130 status = "disabled"; 131 }; 132 133 pll: pll@0 { 134 #clock-cells = <0>; 135 compatible = "st,stm32h7rs-pll-clock"; 136 reg = <0>; 137 status = "disabled"; 138 }; 139 140 pll2: pll@1 { 141 #clock-cells = <0>; 142 compatible = "st,stm32h7rs-pll-clock"; 143 reg = <1>; 144 status = "disabled"; 145 }; 146 147 pll3: pll@2 { 148 #clock-cells = <0>; 149 compatible = "st,stm32h7rs-pll-clock"; 150 reg = <2>; 151 status = "disabled"; 152 }; 153 154 perck: perck { 155 #clock-cells = <0>; 156 compatible = "st,stm32-clock-mux"; 157 status = "disabled"; 158 }; 159 }; 160 161 soc { 162 flash: flash-controller@52002000 { 163 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; 164 reg = <0x52002000 0x400>; 165 interrupts = <8 0>; 166 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>; 167 168 #address-cells = <1>; 169 #size-cells = <1>; 170 171 flash0: flash@8000000 { 172 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 173 write-block-size = <32>; 174 erase-block-size = <DT_SIZE_K(8)>; 175 /* maximum erase time for a 8K sector */ 176 max-erase-time = <3>; 177 }; 178 }; 179 180 rcc: rcc@58024400 { 181 compatible = "st,stm32h7rs-rcc"; 182 #clock-cells = <2>; 183 reg = <0x58024400 0x400>; 184 185 rctl: reset-controller { 186 compatible = "st,stm32-rcc-rctl"; 187 #reset-cells = <1>; 188 }; 189 }; 190 191 exti: interrupt-controller@58000000 { 192 compatible = "st,stm32h7rs-exti", "st,stm32-exti"; 193 interrupt-controller; 194 #interrupt-cells = <1>; 195 #address-cells = <1>; 196 reg = <0x58000000 0x400>; 197 /* SBS for interrupt */ 198 num-lines = <16>; 199 interrupts = <16 0>, <17 0>, <18 0>, <19 0>, 200 <20 0>, <21 0>, <22 0>, <23 0>, 201 <24 0>, <25 0>, <26 0>, <27 0>, 202 <28 0>, <29 0>, <30 0>, <31 0>; 203 interrupt-names = "line0", "line1", "line2", "line3", 204 "line4", "line5", "line6", "line7", 205 "line8", "line9", "line10", "line11", 206 "line12", "line13", "line14", "line15"; 207 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 208 <4 1>, <5 1>, <6 1>, <7 1>, 209 <8 1>, <9 1>, <10 1>, <11 1>, 210 <12 1>, <13 1>, <14 1>, <15 1>; 211 }; 212 213 pinctrl: pin-controller@58020000 { 214 compatible = "st,stm32-pinctrl"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 reg = <0x58020000 0x2400>; 218 219 gpioa: gpio@58020000 { 220 compatible = "st,stm32-gpio"; 221 gpio-controller; 222 #gpio-cells = <2>; 223 reg = <0x58020000 0x400>; 224 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>; 225 }; 226 227 gpiob: gpio@58020400 { 228 compatible = "st,stm32-gpio"; 229 gpio-controller; 230 #gpio-cells = <2>; 231 reg = <0x58020400 0x400>; 232 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>; 233 }; 234 235 gpioc: gpio@58020800 { 236 compatible = "st,stm32-gpio"; 237 gpio-controller; 238 #gpio-cells = <2>; 239 reg = <0x58020800 0x400>; 240 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>; 241 }; 242 243 gpiod: gpio@58020C00 { 244 compatible = "st,stm32-gpio"; 245 gpio-controller; 246 #gpio-cells = <2>; 247 reg = <0x58020C00 0x400>; 248 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>; 249 }; 250 251 gpioe: gpio@58021000 { 252 compatible = "st,stm32-gpio"; 253 gpio-controller; 254 #gpio-cells = <2>; 255 reg = <0x58021000 0x400>; 256 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>; 257 }; 258 259 gpiof: gpio@58021400 { 260 compatible = "st,stm32-gpio"; 261 gpio-controller; 262 #gpio-cells = <2>; 263 reg = <0x58021400 0x400>; 264 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>; 265 }; 266 267 gpiog: gpio@58021800 { 268 compatible = "st,stm32-gpio"; 269 gpio-controller; 270 #gpio-cells = <2>; 271 reg = <0x58021800 0x400>; 272 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>; 273 }; 274 275 gpioh: gpio@58021c00 { 276 compatible = "st,stm32-gpio"; 277 gpio-controller; 278 #gpio-cells = <2>; 279 reg = <0x58021c00 0x400>; 280 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>; 281 }; 282 283 gpiom: gpio@58023000 { 284 compatible = "st,stm32-gpio"; 285 gpio-controller; 286 #gpio-cells = <2>; 287 reg = <0x58023000 0x400>; 288 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00001000>; 289 }; 290 291 gpion: gpio@58023400 { 292 compatible = "st,stm32-gpio"; 293 gpio-controller; 294 #gpio-cells = <2>; 295 reg = <0x58023400 0x400>; 296 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00002000>; 297 }; 298 299 gpioo: gpio@58023800 { 300 compatible = "st,stm32-gpio"; 301 gpio-controller; 302 #gpio-cells = <2>; 303 reg = <0x58023800 0x400>; 304 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00004000>; 305 }; 306 307 gpiop: gpio@58023c00 { 308 compatible = "st,stm32-gpio"; 309 gpio-controller; 310 #gpio-cells = <2>; 311 reg = <0x58023c00 0x400>; 312 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00008000>; 313 }; 314 }; 315 316 usart1: serial@42001000 { 317 compatible = "st,stm32-usart", "st,stm32-uart"; 318 reg = <0x42001000 0x400>; 319 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>; 320 resets = <&rctl STM32_RESET(APB2, 4U)>; 321 interrupts = <82 0>; 322 status = "disabled"; 323 }; 324 usart2: serial@40004400 { 325 compatible = "st,stm32-usart", "st,stm32-uart"; 326 reg = <0x40004400 0x400>; 327 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; 328 resets = <&rctl STM32_RESET(APB1L, 17U)>; 329 interrupts = <83 0>; 330 status = "disabled"; 331 }; 332 usart3: serial@40004800 { 333 compatible = "st,stm32-usart", "st,stm32-uart"; 334 reg = <0x40004800 0x400>; 335 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; 336 resets = <&rctl STM32_RESET(APB1L, 18U)>; 337 interrupts = <84 0>; 338 status = "disabled"; 339 }; 340 uart4: serial@40004c00 { 341 compatible ="st,stm32-uart"; 342 reg = <0x40004c00 0x400>; 343 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; 344 resets = <&rctl STM32_RESET(APB1L, 19U)>; 345 interrupts = <85 0>; 346 status = "disabled"; 347 }; 348 uart5: serial@40005000 { 349 compatible = "st,stm32-uart"; 350 reg = <0x40005000 0x400>; 351 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; 352 resets = <&rctl STM32_RESET(APB1L, 20U)>; 353 interrupts = <86 0>; 354 status = "disabled"; 355 }; 356 uart7: serial@40007800 { 357 compatible = "st,stm32-uart"; 358 reg = <0x40007800 0x400>; 359 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>; 360 resets = <&rctl STM32_RESET(APB1L, 30U)>; 361 interrupts = <87 0>; 362 status = "disabled"; 363 }; 364 uart8: serial@40007c00 { 365 compatible = "st,stm32-uart"; 366 reg = <0x40007c00 0x400>; 367 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>; 368 resets = <&rctl STM32_RESET(APB1L, 31U)>; 369 interrupts = <88 0>; 370 status = "disabled"; 371 }; 372 373 lpuart1: serial@58000c00 { 374 compatible = "st,stm32-lpuart", "st,stm32-uart"; 375 reg = <0x58000c00 0x400>; 376 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>; 377 resets = <&rctl STM32_RESET(APB4, 3U)>; 378 interrupts = <131 0>; 379 status = "disabled"; 380 }; 381 382 i2c1: i2c@40005400 { 383 compatible = "st,stm32-i2c-v2"; 384 clock-frequency = <I2C_BITRATE_STANDARD>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 reg = <0x40005400 0x400>; 388 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; 389 interrupts = <76 0>, <77 0>; 390 interrupt-names = "event", "error"; 391 status = "disabled"; 392 }; 393 394 i2c2: i2c@40005800 { 395 compatible = "st,stm32-i2c-v2"; 396 clock-frequency = <I2C_BITRATE_STANDARD>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 reg = <0x40005800 0x400>; 400 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; 401 interrupts = <78 0>, <79 0>; 402 interrupt-names = "event", "error"; 403 status = "disabled"; 404 }; 405 406 i2c3: i2c@40005c00 { 407 compatible = "st,stm32-i2c-v2"; 408 clock-frequency = <I2C_BITRATE_STANDARD>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 reg = <0x40005c00 0x400>; 412 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; 413 interrupts = <80 0>, <81 0>; 414 interrupt-names = "event", "error"; 415 status = "disabled"; 416 }; 417 418 spi1: spi@42003000 { 419 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <0x42003000 0x400>; 423 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, 424 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 425 interrupts = <58 0>; 426 status = "disabled"; 427 }; 428 429 spi2: spi@40003800 { 430 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 reg = <0x40003800 0x400>; 434 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>, 435 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; 436 interrupts = <59 0>; 437 status = "disabled"; 438 }; 439 440 spi3: spi@40003c00 { 441 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 reg = <0x40003c00 0x400>; 445 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>, 446 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; 447 interrupts = <60 0>; 448 status = "disabled"; 449 }; 450 451 spi4: spi@42003400 { 452 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 reg = <0x42003400 0x400>; 456 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; 457 interrupts = <61 0>; 458 status = "disabled"; 459 }; 460 461 spi5: spi@42005000 { 462 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 reg = <0x42005000 0x400>; 466 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>; 467 interrupts = <62 0>; 468 status = "disabled"; 469 }; 470 471 i2s1: i2s@40013000 { 472 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <0x40013000 0x400>; 476 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, 477 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 478 interrupts = <35 3>; 479 status = "disabled"; 480 }; 481 482 iwdg: iwdg1: watchdog@58004800 { 483 compatible = "st,stm32-watchdog"; 484 reg = <0x58004800 0x400>; 485 interrupts = <3 0>; 486 status = "disabled"; 487 }; 488 489 wwdg: wwdg1: watchdog@40002c00 { 490 compatible = "st,stm32-window-watchdog"; 491 reg = <0x40002c00 0x1000>; 492 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; 493 interrupts = <4 7>; 494 status = "disabled"; 495 }; 496 497 timers1: timers@42000000 { 498 compatible = "st,stm32-timers"; 499 reg = <0x42000000 0x400>; 500 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>; 501 resets = <&rctl STM32_RESET(APB2, 0U)>; 502 interrupts = <47 0>, <48 0>, <49 0>, <50 0>; 503 interrupt-names = "brk", "up", "trgcom", "cc"; 504 st,prescaler = <0>; 505 status = "disabled"; 506 507 pwm { 508 compatible = "st,stm32-pwm"; 509 status = "disabled"; 510 #pwm-cells = <3>; 511 }; 512 }; 513 514 timers2: timers@40000000 { 515 compatible = "st,stm32-timers"; 516 reg = <0x40000000 0x400>; 517 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; 518 resets = <&rctl STM32_RESET(APB1L, 0U)>; 519 interrupts = <51 0>; 520 interrupt-names = "global"; 521 st,prescaler = <0>; 522 status = "disabled"; 523 524 pwm { 525 compatible = "st,stm32-pwm"; 526 status = "disabled"; 527 #pwm-cells = <3>; 528 }; 529 530 counter { 531 compatible = "st,stm32-counter"; 532 status = "disabled"; 533 }; 534 }; 535 536 timers3: timers@40000400 { 537 compatible = "st,stm32-timers"; 538 reg = <0x40000400 0x400>; 539 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; 540 resets = <&rctl STM32_RESET(APB1L, 1U)>; 541 interrupts = <52 0>; 542 interrupt-names = "global"; 543 st,prescaler = <0>; 544 status = "disabled"; 545 546 pwm { 547 compatible = "st,stm32-pwm"; 548 status = "disabled"; 549 #pwm-cells = <3>; 550 }; 551 552 counter { 553 compatible = "st,stm32-counter"; 554 status = "disabled"; 555 }; 556 }; 557 558 timers4: timers@40000800 { 559 compatible = "st,stm32-timers"; 560 reg = <0x40000800 0x400>; 561 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; 562 resets = <&rctl STM32_RESET(APB1L, 2U)>; 563 interrupts = <53 0>; 564 interrupt-names = "global"; 565 st,prescaler = <0>; 566 status = "disabled"; 567 568 pwm { 569 compatible = "st,stm32-pwm"; 570 status = "disabled"; 571 #pwm-cells = <3>; 572 }; 573 574 counter { 575 compatible = "st,stm32-counter"; 576 status = "disabled"; 577 }; 578 }; 579 580 timers5: timers@40000c00 { 581 compatible = "st,stm32-timers"; 582 reg = <0x40000c00 0x400>; 583 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; 584 resets = <&rctl STM32_RESET(APB1L, 3U)>; 585 interrupts = <54 0>; 586 interrupt-names = "global"; 587 st,prescaler = <0>; 588 status = "disabled"; 589 590 pwm { 591 compatible = "st,stm32-pwm"; 592 status = "disabled"; 593 #pwm-cells = <3>; 594 }; 595 596 counter { 597 compatible = "st,stm32-counter"; 598 status = "disabled"; 599 }; 600 }; 601 602 timers6: timers@40001000 { 603 compatible = "st,stm32-timers"; 604 reg = <0x40001000 0x400>; 605 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; 606 resets = <&rctl STM32_RESET(APB1L, 4U)>; 607 interrupts = <55 0>; 608 interrupt-names = "global"; 609 st,prescaler = <0>; 610 status = "disabled"; 611 612 counter { 613 compatible = "st,stm32-counter"; 614 status = "disabled"; 615 }; 616 }; 617 618 timers7: timers@40001400 { 619 compatible = "st,stm32-timers"; 620 reg = <0x40001400 0x400>; 621 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; 622 resets = <&rctl STM32_RESET(APB1L, 5U)>; 623 interrupts = <56 0>; 624 interrupt-names = "global"; 625 st,prescaler = <0>; 626 status = "disabled"; 627 628 counter { 629 compatible = "st,stm32-counter"; 630 status = "disabled"; 631 }; 632 }; 633 634 timers9: timers@42004c00 { 635 compatible = "st,stm32-timers"; 636 reg = <0x42004c00 0x400>; 637 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>; 638 resets = <&rctl STM32_RESET(APB2, 19U)>; 639 interrupts = <57 0>; 640 interrupt-names = "global"; 641 st,prescaler = <0>; 642 status = "disabled"; 643 644 counter { 645 compatible = "st,stm32-counter"; 646 status = "disabled"; 647 }; 648 }; 649 650 timers15: timers@42004000 { 651 compatible = "st,stm32-timers"; 652 reg = <0x42004000 0x400>; 653 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; 654 resets = <&rctl STM32_RESET(APB2, 16U)>; 655 interrupts = <116 0>; 656 interrupt-names = "global"; 657 st,prescaler = <0>; 658 status = "disabled"; 659 660 pwm { 661 compatible = "st,stm32-pwm"; 662 status = "disabled"; 663 #pwm-cells = <3>; 664 }; 665 666 counter { 667 compatible = "st,stm32-counter"; 668 status = "disabled"; 669 }; 670 }; 671 672 timers16: timers@42004400 { 673 compatible = "st,stm32-timers"; 674 reg = <0x42004400 0x400>; 675 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; 676 resets = <&rctl STM32_RESET(APB2, 17U)>; 677 interrupts = <117 0>; 678 interrupt-names = "global"; 679 st,prescaler = <0>; 680 status = "disabled"; 681 682 pwm { 683 compatible = "st,stm32-pwm"; 684 status = "disabled"; 685 #pwm-cells = <3>; 686 }; 687 688 counter { 689 compatible = "st,stm32-counter"; 690 status = "disabled"; 691 }; 692 }; 693 694 timers17: timers@42004800 { 695 compatible = "st,stm32-timers"; 696 reg = <0x42004800 0x400>; 697 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; 698 resets = <&rctl STM32_RESET(APB2, 18U)>; 699 interrupts = <118 0>; 700 interrupt-names = "global"; 701 st,prescaler = <0>; 702 status = "disabled"; 703 704 pwm { 705 compatible = "st,stm32-pwm"; 706 status = "disabled"; 707 #pwm-cells = <3>; 708 }; 709 710 counter { 711 compatible = "st,stm32-counter"; 712 status = "disabled"; 713 }; 714 }; 715 716 lptim1: timers@40002400 { 717 compatible = "st,stm32-lptim"; 718 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 reg = <0x40002400 0x400>; 722 interrupts = <119 1>; 723 interrupt-names = "wakeup"; 724 status = "disabled"; 725 }; 726 727 adc1: adc@40022000 { 728 compatible = "st,stm32-adc"; 729 reg = <0x40022000 0x400>; 730 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; 731 interrupts = <38 0>; 732 status = "disabled"; 733 #io-channel-cells = <1>; 734 resolutions = <STM32_ADC_RES(12, 0x00) 735 STM32_ADC_RES(10, 0x01) 736 STM32_ADC_RES(8, 0x2) 737 STM32_ADC_RES(6, 0x3)>; 738 sampling-times = <3 7 13 25 48 93 248 641>; 739 st,adc-sequencer = <FULLY_CONFIGURABLE>; 740 }; 741 742 adc2: adc@40022100 { 743 compatible = "st,stm32-adc"; 744 reg = <0x40022100 0x400>; 745 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; 746 interrupts = <38 0>; 747 status = "disabled"; 748 #io-channel-cells = <1>; 749 resolutions = <STM32_ADC_RES(12, 0x00) 750 STM32_ADC_RES(10, 0x01) 751 STM32_ADC_RES(8, 0x02) 752 STM32_ADC_RES(6, 0x03)>; 753 sampling-times = <3 7 13 25 48 93 248 641>; 754 st,adc-sequencer = <FULLY_CONFIGURABLE>; 755 }; 756 757 rng: rng@48020000 { 758 compatible = "st,stm32-rng"; 759 reg = <0x48020000 0x400>; 760 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>; 761 interrupts = <37 0>; 762 status = "disabled"; 763 }; 764 }; 765 766 die_temp: dietemp { 767 compatible = "st,stm32-temp-cal"; 768 ts-cal1-addr = <0x08FFF814>; 769 ts-cal2-addr = <0x08FFF818>; 770 ts-cal1-temp = <30>; 771 ts-cal2-temp = <130>; 772 ts-cal-vrefanalog = <3300>; 773 ts-cal-resolution = <12>; 774 io-channels = <&adc1 16>; 775 status = "disabled"; 776 }; 777 778 vbat: vbat { 779 compatible = "st,stm32-vbat"; 780 ratio = <4>; 781 status = "disabled"; 782 io-channels = <&adc2 16>; 783 }; 784 785 vref: vref { 786 compatible = "st,stm32-vref"; 787 vrefint-cal-addr = <0x08fff810>; 788 vrefint-cal-mv = <3300>; 789 status = "disabled"; 790 io-channels = <&adc1 17>; 791 }; 792}; 793 794&nvic { 795 arm,num-irq-priority-bits = <4>; 796}; 797
