1/* 2 * Copyright (c) 2021 Electrolance Solutions 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/h7/stm32h7.dtsi> 8#include <zephyr/dt-bindings/display/panel.h> 9#include <zephyr/dt-bindings/flash_controller/ospi.h> 10 11/delete-node/ &adc3; 12 13/ { 14 soc { 15 compatible = "st,stm32h7a3", "st,stm32h7", "simple-bus"; 16 17 flash-controller@52002000 { 18 flash0: flash@8000000 { 19 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 20 write-block-size = <16>; 21 erase-block-size = <DT_SIZE_K(8)>; 22 /* maximum erase time for a 8K sector */ 23 max-erase-time = <3>; 24 }; 25 }; 26 27 dmamux1: dmamux@40020800 { 28 dma-requests= <107>; 29 }; 30 31 dmamux2: dmamux@58025800 { 32 dma-requests= <107>; 33 }; 34 35 usbotg_hs: usb@40040000 { 36 compatible = "st,stm32-otghs"; 37 reg = <0x40040000 0x40000>; 38 interrupts = <77 0>, <74 0>, <75 0>; 39 interrupt-names = "otghs", "ep1_out", "ep1_in"; 40 num-bidir-endpoints = <9>; 41 ram-size = <4096>; 42 maximum-speed = "full-speed"; 43 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>, 44 <&rcc STM32_SRC_HSI48 USB_SEL(3)>; 45 phys = <&otghs_fs_phy>; 46 status = "disabled"; 47 }; 48 49 ltdc: display-controller@50001000 { 50 compatible = "st,stm32-ltdc"; 51 reg = <0x50001000 0x200>; 52 interrupts = <88 0>, <89 0>; 53 interrupt-names = "ltdc", "ltdc_er"; 54 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>; 55 status = "disabled"; 56 }; 57 58 octospi1: octospi@52005000 { 59 compatible = "st,stm32-ospi"; 60 reg = <0x52005000 0x1000>; 61 interrupts = <92 0>; 62 clock-names = "ospix", "ospi-ker"; 63 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>, 64 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 status = "disabled"; 68 }; 69 70 octospi2: octospi@5200a000 { 71 compatible = "st,stm32-ospi"; 72 reg = <0x5200a000 0x1000>; 73 interrupts = <150 0>; 74 clock-names = "ospix", "ospi-ker"; 75 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>, 76 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 status = "disabled"; 80 }; 81 82 i2s6: i2s@58001400 { 83 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 reg = <0x58001400 0x400>; 87 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000020>, 88 <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>; 89 dmas = <&dmamux2 0 12 0x20440 &dmamux2 1 11 0x20480>; 90 dma-names = "tx", "rx"; 91 interrupts = <86 0>; 92 status = "disabled"; 93 }; 94 95 rng: rng@48021800 { 96 nist-config = <0xf00d00>; 97 health-test-magic = <0x17590abc>; 98 health-test-config = <0x72ac>; 99 }; 100 101 digi_die_temp: digi_dietemp@58006800 { 102 compatible = "st,stm32-digi-temp"; 103 reg = <0x58006800 0x400>; 104 interrupts = <147 0>; 105 interrupt-names = "digi_temp"; 106 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x04000000>; 107 status = "disabled"; 108 }; 109 }; 110 111 /* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */ 112 sram0: memory@24000000 { 113 compatible = "mmio-sram"; 114 reg = <0x24000000 DT_SIZE_K(256)>; 115 }; 116 117 /* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */ 118 sram1: memory@24040000 { 119 compatible = "zephyr,memory-region", "mmio-sram"; 120 reg = <0x24040000 DT_SIZE_K(384)>; 121 zephyr,memory-region = "SRAM1"; 122 }; 123 124 /* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */ 125 sram2: memory@240A0000 { 126 compatible = "zephyr,memory-region", "mmio-sram"; 127 reg = <0x240A0000 DT_SIZE_K(384)>; 128 zephyr,memory-region = "SRAM2"; 129 }; 130 131 /* System data RAM accessible over AHB bus: SRAM1 in CD domain */ 132 sram3: memory@30000000 { 133 compatible = "zephyr,memory-region", "mmio-sram"; 134 reg = <0x30000000 DT_SIZE_K(64)>; 135 zephyr,memory-region = "SRAM3"; 136 }; 137 138 /* System data RAM accessible over AHB bus: SRAM2 in CD domain */ 139 sram4: memory@30010000 { 140 compatible = "zephyr,memory-region", "mmio-sram"; 141 reg = <0x30010000 DT_SIZE_K(64)>; 142 zephyr,memory-region = "SRAM4"; 143 }; 144 145 /* System data RAM accessible over AHB bus: SRD SRAM in SRD domain */ 146 sram5: memory@38000000 { 147 compatible = "zephyr,memory-region", "mmio-sram"; 148 reg = <0x38000000 DT_SIZE_K(32)>; 149 zephyr,memory-region = "SRAM5"; 150 }; 151 152 dtcm: memory@20000000 { 153 compatible = "zephyr,memory-region", "arm,dtcm"; 154 reg = <0x20000000 DT_SIZE_K(128)>; 155 zephyr,memory-region = "DTCM"; 156 }; 157 158 itcm: memory@0 { 159 compatible = "zephyr,memory-region", "arm,itcm"; 160 reg = <0x00000000 DT_SIZE_K(64)>; 161 zephyr,memory-region = "ITCM"; 162 }; 163 164 ext_memory2: memory@70000000 { 165 compatible = "zephyr,memory-region"; 166 reg = <0x70000000 DT_SIZE_M(256)>; /* max addressable area */ 167 zephyr,memory-region = "EXTMEM2"; 168 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; 169 }; 170 171 otghs_fs_phy: otghs_fs_phy { 172 compatible = "usb-nop-xceiv"; 173 #phy-cells = <0>; 174 }; 175 176 die_temp: dietemp { 177 ts-cal1-addr = <0x08FFF814>; 178 ts-cal2-addr = <0x08FFF818>; 179 io-channels = <&adc2 18>; 180 ts-cal2-temp = <130>; 181 }; 182 183 vref: vref { 184 vrefint-cal-addr = <0x08FFF810>; 185 io-channels = <&adc2 19>; 186 }; 187 188 vbat: vbat { 189 io-channels = <&adc2 14>; 190 }; 191}; 192
