1/*
2 * Copyright (c) 2023 Rahul Arasikere
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f7/stm32f7.dtsi>
8
9/ {
10	/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
11	 * 16KB SRAM2 @ 2007C000
12	 */
13
14	sram0: memory@20020000 {
15		compatible = "zephyr,memory-region", "mmio-sram";
16		reg = <0x20020000 DT_SIZE_K(384)>;
17		zephyr,memory-region = "SRAM0";
18	};
19
20	dtcm: memory@20000000 {
21		compatible = "zephyr,memory-region", "arm,dtcm";
22		reg = <0x20000000 DT_SIZE_K(128)>;
23		zephyr,memory-region = "DTCM";
24	};
25
26	soc {
27		compatible = "st,stm32f765", "st,stm32f7", "simple-bus";
28
29		pinctrl: pin-controller@40020000 {
30			reg = <0x40020000 0x2C00>;
31
32			gpioj: gpio@40022400 {
33				compatible = "st,stm32-gpio";
34				gpio-controller;
35				#gpio-cells = <2>;
36				reg = <0x40022400 0x400>;
37				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
38			};
39
40			gpiok: gpio@40022800 {
41				compatible = "st,stm32-gpio";
42				gpio-controller;
43				#gpio-cells = <2>;
44				reg = <0x40022800 0x400>;
45				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
46			};
47		};
48
49		i2c4: i2c@40006000 {
50			compatible = "st,stm32-i2c-v2";
51			clock-frequency = <I2C_BITRATE_STANDARD>;
52			#address-cells = <1>;
53			#size-cells = <0>;
54			reg = <0x40006000 0x400>;
55			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
56			interrupts = <95 0>, <96 0>;
57			interrupt-names = "event", "error";
58			status = "disabled";
59		};
60
61		spi6: spi@40015400 {
62			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
63			#address-cells = <1>;
64			#size-cells = <0>;
65			reg = <0x40015400 0x400>;
66			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
67			interrupts = <86 5>;
68			status = "disabled";
69		};
70
71		mac: ethernet@40028000 {
72			compatible = "st,stm32-ethernet";
73			reg = <0x40028000 0x8000>;
74			interrupts = <61 0>;
75			clock-names = "stmmaceth", "mac-clk-tx",
76				      "mac-clk-rx", "mac-clk-ptp";
77			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
78				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
79				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
80				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
81			status = "disabled";
82		};
83
84		sdmmc2: sdmmc@40011c00 {
85			compatible = "st,stm32-sdmmc";
86			reg = <0x40011c00 0x400>;
87			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
88				 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
89			resets = <&rctl STM32_RESET(APB2, 7U)>;
90			interrupts = <103 0>;
91			status = "disabled";
92		};
93
94	};
95
96	smbus4: smbus4 {
97		compatible = "st,stm32-smbus";
98		#address-cells = <1>;
99		#size-cells = <0>;
100		i2c = <&i2c4>;
101		status = "disabled";
102	};
103};
104