1/*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f0/stm32f031.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32f042", "st,stm32f0", "simple-bus";
12
13		clocks {
14			clk_hsi48: clk-hsi48 {
15				#clock-cells = <0>;
16				compatible = "fixed-clock";
17				clock-frequency = <DT_FREQ_M(48)>;
18				status = "disabled";
19			};
20		};
21
22		usart2: serial@40004400 {
23			compatible = "st,stm32-usart", "st,stm32-uart";
24			reg = <0x40004400 0x400>;
25			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
26			resets = <&rctl STM32_RESET(APB1, 17U)>;
27			interrupts = <28 0>;
28			status = "disabled";
29		};
30
31		spi2: spi@40003800 {
32			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
33			#address-cells = <1>;
34			#size-cells = <0>;
35			reg = <0x40003800 0x400>;
36			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
37			interrupts = <26 3>;
38			status = "disabled";
39		};
40
41		can1: can@40006400 {
42			compatible = "st,stm32-bxcan";
43			reg = <0x40006400 0x400>;
44			interrupts = <30 0>;
45			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
46			status = "disabled";
47		};
48
49		timers15: timers@40014000 {
50			compatible = "st,stm32-timers";
51			reg = <0x40014000 0x400>;
52			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
53			resets = <&rctl STM32_RESET(APB2, 16U)>;
54			interrupts = <20 0>;
55			interrupt-names = "global";
56			st,prescaler = <0>;
57			status = "disabled";
58
59			pwm {
60				compatible = "st,stm32-pwm";
61				status = "disabled";
62				#pwm-cells = <3>;
63			};
64		};
65
66		usb: usb@40005c00 {
67			compatible = "st,stm32-usb";
68			reg = <0x40005c00 0x400>;
69			interrupts = <31 0>;
70			interrupt-names = "usb";
71			num-bidir-endpoints = <8>;
72			ram-size = <1024>;
73			phys = <&usb_fs_phy>;
74			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
75				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
76			status = "disabled";
77		};
78	};
79
80	usb_fs_phy: usbphy {
81		compatible = "usb-nop-xceiv";
82		#phy-cells = <0>;
83	};
84};
85