1/*
2 * Copyright (c) 2023 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm64/armv8-r.dtsi>
9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-r52";
20			reg = <0>;
21		};
22	};
23
24	timer {
25		compatible = "arm,armv8-timer";
26		interrupt-parent = <&gic>;
27		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
28				 IRQ_DEFAULT_PRIORITY>,
29				<GIC_PPI 14 IRQ_TYPE_LEVEL
30				 IRQ_DEFAULT_PRIORITY>,
31				<GIC_PPI 11 IRQ_TYPE_LEVEL
32				 IRQ_DEFAULT_PRIORITY>,
33				<GIC_PPI 10 IRQ_TYPE_LEVEL
34				 IRQ_DEFAULT_PRIORITY>;
35	};
36
37	soc {
38		interrupt-parent = <&gic>;
39
40		sram0: memory@40040000 {
41			compatible = "mmio-sram";
42			reg = <0x40040000 0x100000>;
43		};
44
45		gic: interrupt-controller@f0000000 {
46			compatible = "arm,gic-v3", "arm,gic";
47			reg = <0xf0000000 0x1000>,
48				  <0xf0100000 0x20000>;
49			interrupt-controller;
50			#interrupt-cells = <4>;
51			status = "okay";
52		};
53
54		scif0: serial@e6e60000 {
55			compatible = "renesas,rcar-scif";
56			reg = <0xe6e60000 0x64>;
57			current-speed = <115200>;
58			status = "disabled";
59		};
60
61		scif3: serial@e6c50000 {
62			compatible = "renesas,rcar-scif";
63			reg = <0xe6c50000 0x64>;
64			current-speed = <115200>;
65			status = "disabled";
66		};
67	};
68};
69