1/* 2 * Copyright 2020 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv6-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/kinetis_sim.h> 11#include <zephyr/dt-bindings/clock/kinetis_mcg.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/pwm/pwm.h> 15 16/ { 17 chosen { 18 zephyr,entropy = &trng; 19 zephyr,flash-controller = &ftfa; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-m0+"; 29 reg = <0>; 30 }; 31 }; 32 33 sram0: memory@20000000 { 34 compatible = "mmio-sram"; 35 reg = <0x20000000 DT_SIZE_K(96)>; 36 }; 37 38 /* Dummy pinctrl node, filled with pin mux options at board level */ 39 pinctrl: pinctrl { 40 compatible = "nxp,kinetis-pinctrl"; 41 status = "okay"; 42 }; 43 44 soc { 45 mcg: clock-controller@40064000 { 46 compatible = "nxp,kinetis-mcg"; 47 reg = <0x40064000 0x13>; 48 #clock-cells = <1>; 49 }; 50 51 osc: clock-controller@40065000 { 52 compatible = "nxp,kw41z-osc"; 53 reg = <0x40065000 0x4>; 54 enable-external-reference; 55 }; 56 57 rtc: rtc@4003d000 { 58 compatible = "nxp,kinetis-rtc"; 59 reg = <0x4003d000 0x20>; 60 interrupts = <20 0>; 61 clock-frequency = <32768>; 62 prescaler = <32768>; 63 }; 64 65 sim: sim@40047000 { 66 compatible = "nxp,kinetis-sim"; 67 reg = <0x40047000 0x1060>; 68 #clock-cells = <3>; 69 70 core_clk { 71 compatible = "fixed-factor-clock"; 72 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 73 clock-div = <1>; 74 #clock-cells = <0>; 75 }; 76 77 flash_clk { 78 compatible = "fixed-factor-clock"; 79 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 80 clock-div = <2>; 81 #clock-cells = <0>; 82 }; 83 }; 84 85 ftfa: flash-controller@40020000 { 86 compatible = "nxp,kinetis-ftfa"; 87 reg = <0x40020000 0x2c>; 88 interrupts = <5 0>; 89 status = "okay"; 90 91 #address-cells = <1>; 92 #size-cells = <1>; 93 94 flash0: flash@0 { 95 compatible = "soc-nv-flash"; 96 reg = <0 DT_SIZE_K(512)>; 97 erase-block-size = <2048>; 98 write-block-size = <4>; 99 }; 100 }; 101 102 i2c0: i2c@40066000 { 103 compatible = "nxp,kinetis-i2c"; 104 clock-frequency = <I2C_BITRATE_STANDARD>; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 reg = <0x40066000 0x1000>; 108 interrupts = <8 0>; 109 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>; 110 status = "disabled"; 111 }; 112 113 i2c1: i2c@40067000 { 114 compatible = "nxp,kinetis-i2c"; 115 clock-frequency = <I2C_BITRATE_STANDARD>; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 reg = <0x40067000 0x1000>; 119 interrupts = <9 0>; 120 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 7>; 121 status = "disabled"; 122 }; 123 124 lpuart0: lpuart@40054000 { 125 compatible = "nxp,kinetis-lpuart"; 126 reg = <0x40054000 0x18>; 127 interrupts = <12 0>; 128 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>; 129 130 status = "disabled"; 131 }; 132 133 porta: pinmux@40049000 { 134 compatible = "nxp,kinetis-pinmux"; 135 reg = <0x40049000 0xa4>; 136 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; 137 }; 138 139 portb: pinmux@4004a000 { 140 compatible = "nxp,kinetis-pinmux"; 141 reg = <0x4004a000 0xa4>; 142 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; 143 }; 144 145 portc: pinmux@4004b000 { 146 compatible = "nxp,kinetis-pinmux"; 147 reg = <0x4004b000 0xa4>; 148 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; 149 }; 150 151 gpioa: gpio@400ff000 { 152 compatible = "nxp,kinetis-gpio"; 153 status = "disabled"; 154 reg = <0x400ff000 0x40>; 155 interrupts = <30 2>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 nxp,kinetis-port = <&porta>; 159 }; 160 161 gpiob: gpio@400ff040 { 162 compatible = "nxp,kinetis-gpio"; 163 status = "disabled"; 164 reg = <0x400ff040 0x40>; 165 gpio-controller; 166 #gpio-cells = <2>; 167 nxp,kinetis-port = <&portb>; 168 }; 169 170 gpioc: gpio@400ff080 { 171 compatible = "nxp,kinetis-gpio"; 172 status = "disabled"; 173 reg = <0x400ff080 0x40>; 174 interrupts = <31 2>; 175 gpio-controller; 176 #gpio-cells = <2>; 177 nxp,kinetis-port = <&portc>; 178 }; 179 180 spi0: spi@4002c000 { 181 compatible = "nxp,kinetis-dspi"; 182 reg = <0x4002c000 0x9C>; 183 interrupts = <10 3>; 184 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>; 185 status = "disabled"; 186 187 #address-cells = <1>; 188 #size-cells = <0>; 189 }; 190 191 spi1: spi@4002d000 { 192 compatible = "nxp,kinetis-dspi"; 193 reg = <0x4002d000 0x9C>; 194 interrupts = <29 3>; 195 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>; 196 status = "disabled"; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 }; 200 201 tpm0: pwm@40038000 { 202 compatible = "nxp,kinetis-tpm"; 203 reg = <0x40038000 0x88>; 204 interrupts = <0x84 0>; 205 /* channel information needed - fixme */ 206 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 24>; 207 status = "disabled"; 208 #pwm-cells = <3>; 209 }; 210 211 tpm1: pwm@40039000 { 212 compatible = "nxp,kinetis-tpm"; 213 reg = <0x40039000 0x88>; 214 interrupts = <0x88 0>; 215 /* channel information needed - fixme */ 216 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 25>; 217 status = "disabled"; 218 #pwm-cells = <3>; 219 }; 220 221 tpm2: pwm@4003a000 { 222 compatible = "nxp,kinetis-tpm"; 223 reg = <0x4003a000 0x88>; 224 interrupts = <0x8C 0>; 225 /* channel information needed - fixme */ 226 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 26>; 227 status = "disabled"; 228 #pwm-cells = <3>; 229 }; 230 231 adc0: adc@4003b000{ 232 compatible = "nxp,kinetis-adc16"; 233 reg = <0x4003b000 0x70>; 234 interrupts = <15 0>; 235 status = "disabled"; 236 #io-channel-cells = <1>; 237 }; 238 239 trng: random@40029000 { 240 compatible = "nxp,kinetis-trng"; 241 reg = <0x40029000 0x1000>; 242 status = "okay"; 243 interrupts = <13 0>; 244 }; 245 246 ieee802154: ieee802154@4005d000 { 247 compatible = "nxp,kw41z-ieee802154"; 248 reg = <0x4005d000 0x1000>; 249 status = "disabled"; 250 }; 251 }; 252}; 253 254&nvic { 255 arm,num-irq-priority-bits = <2>; 256}; 257
