1/* SPDX-License-Identifier: Apache-2.0 */ 2 3#include <mem.h> 4#include "armv6-m.dtsi" 5#include <zephyr/dt-bindings/adc/adc.h> 6#include <zephyr/dt-bindings/clock/kinetis_sim.h> 7#include <zephyr/dt-bindings/clock/kinetis_mcg.h> 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pwm/pwm.h> 11 12/ { 13 chosen { 14 zephyr,entropy = &trng; 15 }; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-m0+"; 24 reg = <0>; 25 }; 26 }; 27 28 sram0: memory@20000000 { 29 compatible = "mmio-sram"; 30 reg = <0x20000000 DT_SIZE_K(16)>; 31 }; 32 33 /* Dummy pinctrl node, filled with pin mux options at board level */ 34 pinctrl: pinctrl { 35 compatible = "nxp,kinetis-pinctrl"; 36 status = "okay"; 37 }; 38 39 soc { 40 mcg: clock-controller@40064000 { 41 compatible = "nxp,kinetis-mcg"; 42 reg = <0x40064000 0x13>; 43 #clock-cells = <1>; 44 }; 45 46 osc: clock-controller@40065000 { 47 compatible = "nxp,kw41z-osc"; 48 reg = <0x40065000 0x4>; 49 enable-external-reference; 50 }; 51 52 rtc: rtc@4003d000 { 53 compatible = "nxp,kw41z-rtc"; 54 reg = <0x4003d000 0x20>; 55 clock-frequency = <32768>; 56 }; 57 58 sim: sim@40047000 { 59 compatible = "nxp,kinetis-sim"; 60 reg = <0x40047000 0x1060>; 61 #clock-cells = <3>; 62 63 core_clk { 64 compatible = "fixed-factor-clock"; 65 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 66 clock-div = <1>; 67 #clock-cells = <0>; 68 }; 69 70 flash_clk { 71 compatible = "fixed-factor-clock"; 72 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 73 clock-div = <2>; 74 #clock-cells = <0>; 75 }; 76 }; 77 78 ftfa: flash-controller@40020000 { 79 compatible = "nxp,kinetis-ftfa"; 80 reg = <0x40020000 0x2c>; 81 interrupts = <5 0>; 82 status = "disabled"; 83 84 #address-cells = <1>; 85 #size-cells = <1>; 86 87 flash0: flash@0 { 88 compatible = "soc-nv-flash"; 89 reg = <0 DT_SIZE_K(512)>; 90 erase-block-size = <1024>; 91 write-block-size = <4>; 92 }; 93 }; 94 95 i2c0: i2c@40066000 { 96 compatible = "nxp,kinetis-i2c"; 97 clock-frequency = <I2C_BITRATE_STANDARD>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 reg = <0x40066000 0x1000>; 101 interrupts = <8 0>; 102 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>; 103 status = "disabled"; 104 }; 105 106 i2c1: i2c@40067000 { 107 compatible = "nxp,kinetis-i2c"; 108 clock-frequency = <I2C_BITRATE_STANDARD>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 reg = <0x40067000 0x1000>; 112 interrupts = <9 0>; 113 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 7>; 114 status = "disabled"; 115 }; 116 117 lpuart0: lpuart@40054000 { 118 compatible = "nxp,kinetis-lpuart"; 119 reg = <0x40054000 0x18>; 120 interrupts = <12 0>; 121 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>; 122 123 status = "disabled"; 124 }; 125 126 porta: pinmux@40049000 { 127 compatible = "nxp,kinetis-pinmux"; 128 reg = <0x40049000 0xa4>; 129 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; 130 }; 131 132 portb: pinmux@4004a000 { 133 compatible = "nxp,kinetis-pinmux"; 134 reg = <0x4004a000 0xa4>; 135 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; 136 }; 137 138 portc: pinmux@4004b000 { 139 compatible = "nxp,kinetis-pinmux"; 140 reg = <0x4004b000 0xa4>; 141 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; 142 }; 143 144 gpioa: gpio@400ff000 { 145 compatible = "nxp,kinetis-gpio"; 146 status = "disabled"; 147 reg = <0x400ff000 0x40>; 148 interrupts = <30 2>; 149 gpio-controller; 150 #gpio-cells = <2>; 151 nxp,kinetis-port = <&porta>; 152 }; 153 154 gpiob: gpio@400ff040 { 155 compatible = "nxp,kinetis-gpio"; 156 status = "disabled"; 157 reg = <0x400ff040 0x40>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 nxp,kinetis-port = <&portb>; 161 }; 162 163 gpioc: gpio@400ff080 { 164 compatible = "nxp,kinetis-gpio"; 165 status = "disabled"; 166 reg = <0x400ff080 0x40>; 167 interrupts = <31 2>; 168 gpio-controller; 169 #gpio-cells = <2>; 170 nxp,kinetis-port = <&portc>; 171 }; 172 173 spi0: spi@4002c000 { 174 compatible = "nxp,kinetis-dspi"; 175 reg = <0x4002c000 0x9C>; 176 interrupts = <10 3>; 177 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>; 178 status = "disabled"; 179 180 #address-cells = <1>; 181 #size-cells = <0>; 182 }; 183 184 spi1: spi@4002d000 { 185 compatible = "nxp,kinetis-dspi"; 186 reg = <0x4002d000 0x9C>; 187 interrupts = <29 3>; 188 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>; 189 status = "disabled"; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 }; 193 194 tpm0: pwm@40038000 { 195 compatible = "nxp,kw41z-pwm"; 196 reg = <0x40038000 0x88>; 197 prescaler = <2>; 198 period = <1000>; 199 /* channel information needed - fixme */ 200 }; 201 202 tpm1: pwm@40039000 { 203 compatible = "nxp,kw41z-pwm"; 204 reg = <0x40039000 0x88>; 205 prescaler = <2>; 206 period = <1000>; 207 /* channel information needed - fixme */ 208 }; 209 210 tpm2: pwm@4003a000 { 211 compatible = "nxp,kw41z-pwm"; 212 reg = <0x4003a000 0x88>; 213 prescaler = <2>; 214 period = <1000>; 215 /* channel information needed - fixme */ 216 }; 217 218 adc0: adc@4003b000{ 219 compatible = "nxp,kinetis-adc16"; 220 reg = <0x4003b000 0x70>; 221 interrupts = <15 0>; 222 status = "disabled"; 223 #io-channel-cells = <1>; 224 }; 225 226 trng: random@40029000 { 227 compatible = "nxp,kinetis-trng"; 228 reg = <0x40029000 0x1000>; 229 status = "okay"; 230 interrupts = <13 0>; 231 }; 232 }; 233}; 234 235&nvic { 236 arm,num-irq-priority-bits = <2>; 237}; 238
