1/* 2 * SPDX-License-Identifier: Apache-2.0 3 * Copyright (C) 2022, Intel Corporation 4 * Description: 5 * Section of the DTS file containing definitions for the HPS 6 * heavily modified for Zephyr 7 */ 8 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 serial0 = &uart0; 18 serial1 = &uart1; 19 eth0 = &gmac0; 20 usb = &usb1; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a9"; 29 device_type = "cpu"; 30 reg = <0>; 31 /* next-level-cache = <&L2>; */ /*cache driver not available yet */ 32 }; 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a9"; 35 device_type = "cpu"; 36 reg = <1>; 37 /* next-level-cache = <&L2>; */ /*cache driver not available yet */ 38 }; 39 }; 40 41 intc: intc@fffed000 { 42 compatible = "arm,gic-v1", "arm,gic"; 43 #interrupt-cells = <4>; 44 interrupt-controller; 45 reg = <0xfffed000 0x1000>, 46 <0xfffec100 0x100>; 47 }; 48 49 soc { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "simple-bus"; 53 device_type = "soc"; 54 interrupt-parent = <&intc>; 55 ranges; 56 57 L2: l2-cache@fffef000 { 58 compatible = "arm,pl330-cache"; 59 reg = <0xfffef000 0x1000>; 60 interrupts = <0 38 0x04 IRQ_DEFAULT_PRIORITY>; 61 status= "okay"; 62 }; 63 64 clkmgr@ffd04000 { 65 compatible = "altr,clk-mgr"; 66 reg = <0xffd04000 0x1000>; 67 clocks { 68 osc1: osc1 { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 }; 72 osc2: osc2 { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <25000000>; 76 }; 77 f2s_periph_ref_clk: f2s_periph_ref_clk { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <50000000>; 81 }; 82 f2s_sdram_ref_clk: f2s_sdram_ref_clk { 83 #clock-cells = <0>; 84 compatible = "fixed-clock"; 85 clock-frequency = <100000000>; 86 }; 87 }; 88 }; 89 90 sysmgr: sysmgr@ffd08000 { 91 compatible = "altr,sys-mgr", "syscon"; 92 reg = <0xffd08000 0x4000>; 93 status = "okay"; 94 }; 95 ocram: sram@ffff0000 { 96 compatible = "zephyr,memory-region" , "mmio-sram"; 97 reg = <0xffff0000 0x10000>; 98 zephyr,memory-region = "OCRAM"; 99 }; 100 101 arch_timer: timer@fffec200 { 102 compatible = "arm,armv8-timer"; 103 status = "okay"; 104 interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; 105 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE 106 IRQ_DEFAULT_PRIORITY>, 107 <GIC_PPI 14 IRQ_TYPE_EDGE 108 IRQ_DEFAULT_PRIORITY>, 109 <GIC_PPI 11 IRQ_TYPE_EDGE 110 IRQ_DEFAULT_PRIORITY>, 111 <GIC_PPI 10 IRQ_TYPE_EDGE 112 IRQ_DEFAULT_PRIORITY>; 113 reg = <0xfffec200 0x1C>; 114 clocks = <&osc1>; 115 }; 116 117 uart0: serial0@ffc02000 { 118 compatible = "ns16550","snps,dw-apb-uart"; 119 reg = <0xffc02000 0x1000>; 120 interrupts = <0 162 4 IRQ_DEFAULT_PRIORITY>; 121 reg-shift = <2>; 122 clock-frequency = <100000000>; 123 dma-names = "tx", "rx"; 124 }; 125 126 uart1: serial1@ffc03000 { 127 compatible = "ns16550","snps,dw-apb-uart"; 128 reg = <0xffc03000 0x1000>; 129 interrupts = <0 163 4 IRQ_DEFAULT_PRIORITY>; 130 reg-shift = <2>; 131 clock-frequency = <100000000>; 132 dma-names = "tx", "rx"; 133 }; 134 135 gmac0: ethernet@ff700000 { 136 compatible = "snps,ethernet-cyclonev"; 137 reg = <0xff700000 0x2000>; 138 interrupts = <0 115 4 IRQ_DEFAULT_PRIORITY>; 139 emac-index = <0>; 140 status = "disabled"; 141 }; 142 143 gmac1: ethernet@ff702000 { 144 compatible = "snps,ethernet-cyclonev"; 145 reg = <0xff702000 0x2000>; 146 interrupts = <0 120 4 IRQ_DEFAULT_PRIORITY>; 147 emac-index = <1>; 148 status = "disabled"; 149 }; 150 151 gpio0: gpio@ff708000 { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 compatible = "snps,designware-gpio"; 155 reg = <0xff708000 0x1000>; 156 interrupts = <0 164 4 IRQ_DEFAULT_PRIORITY>; 157 status = "disabled"; 158 ngpios = <29>; 159 gpio-controller; 160 #gpio-cells = <2>; 161 }; 162 163 gpio1: gpio@ff709000 { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 compatible = "snps,designware-gpio"; 167 reg = <0xff709000 0x1000>; 168 interrupts = <0 165 4 IRQ_DEFAULT_PRIORITY>; 169 status = "disabled"; 170 ngpios = <29>; 171 gpio-controller; 172 #gpio-cells = <2>; 173 }; 174 175 gpio2: gpio@ff70a000 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "snps,designware-gpio"; 179 reg = <0xff70a000 0x1000>; 180 interrupts = <0 166 4 IRQ_DEFAULT_PRIORITY>; 181 status = "disabled"; 182 ngpios = <27>; 183 gpio-controller; 184 #gpio-cells = <2>; 185 }; 186 187 i2c0: i2c@ffc04000 { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 compatible = "snps,designware-i2c"; 191 reg = <0xffc04000 0x1000>; 192 clock-frequency = <I2C_BITRATE_STANDARD>; 193 interrupts = <0 158 0x4 IRQ_DEFAULT_PRIORITY>; 194 interrupt-parent = <&intc>; 195 status = "okay"; 196 }; 197 198 i2c1: i2c@ffc05000 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "snps,designware-i2c"; 202 reg = <0xffc05000 0x1000>; 203 interrupts = <0 159 0x4 IRQ_DEFAULT_PRIORITY>; 204 status = "disabled"; 205 }; 206 207 i2c2: i2c@ffc06000 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 compatible = "snps,designware-i2c"; 211 reg = <0xffc06000 0x1000>; 212 interrupts = <0 160 0x4 IRQ_DEFAULT_PRIORITY>; 213 status = "disabled"; 214 }; 215 216 i2c3: i2c@ffc07000 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "snps,designware-i2c"; 220 reg = <0xffc07000 0x1000>; 221 interrupts = <0 161 0x4 IRQ_DEFAULT_PRIORITY>; 222 status = "disabled"; 223 }; 224 225 usb0: usb@ffb30000 { 226 compatible = "snps,dwc2"; 227 reg = <0xffb30000 0xffff>; 228 interrupts = <0 127 4 IRQ_DEFAULT_PRIORITY>; 229 interrupt-parent = <&intc>; 230 num-out-eps = <16>; 231 num-in-eps = <16>; 232 ghwcfg1 = <0x00000000>; 233 ghwcfg2 = <0x208ffc90>; 234 ghwcfg4 = <0xfe0f0020>; 235 status = "disabled"; 236 }; 237 238 usb1: usb@ffb40000 { 239 compatible = "snps,dwc2"; 240 reg = <0xffb40000 0xffff>; 241 interrupts = <0 128 4 IRQ_DEFAULT_PRIORITY>; 242 interrupt-parent = <&intc>; 243 num-out-eps = <16>; 244 num-in-eps = <16>; 245 ghwcfg1 = <0x00000000>; 246 ghwcfg2 = <0x208ffc90>; 247 ghwcfg4 = <0xfe0f0020>; 248 status = "okay"; 249 }; 250 251 spi0: spi@fff00000 { 252 compatible = "snps,designware-spi"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 reg = <0xfff00000 0x1000>; 256 fifo-depth = <256>; 257 max-xfer-size = <32>; 258 interrupts = <0 154 4 IRQ_DEFAULT_PRIORITY>; 259 clock-frequency = <200000000>; 260 status = "okay"; 261 }; 262 263 spi1: spi@fff01000 { 264 compatible = "snps,designware-spi"; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 reg = <0xfff01000 0x1000>; 268 fifo-depth = <256>; 269 max-xfer-size = <32>; 270 interrupts = <0 155 4 IRQ_DEFAULT_PRIORITY>; 271 clock-frequency = <200000000>; 272 status = "disabled"; 273 }; 274 }; 275}; 276
