1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9/ {
10	clocks {
11		uartclk: apb-pclk {
12			compatible = "fixed-clock";
13			clock-frequency = <DT_FREQ_M(24)>;
14			#clock-cells = <0>;
15		};
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			compatible = "arm,cortex-m4f";
24			reg = <0>;
25		};
26	};
27
28	/* TCM */
29	tcm: tcm@10000000 {
30		compatible = "zephyr,memory-region";
31		reg = <0x10000000 0x10000>;
32		zephyr,memory-region = "ITCM";
33	};
34
35	/* SRAM */
36	sram0: memory@10010000 {
37		compatible = "mmio-sram";
38		reg = <0x10010000 0xB0000>;
39	};
40
41	xip0: memory@52000000 {
42		compatible = "zephyr,memory-region";
43		reg = <0x52000000 0x2000000>;
44		zephyr,memory-region = "XIP0";
45	};
46
47	xip1: memory@54000000 {
48		compatible = "zephyr,memory-region";
49		reg = <0x54000000 0x2000000>;
50		zephyr,memory-region = "XIP1";
51	};
52
53	xip2: memory@56000000 {
54		compatible = "zephyr,memory-region";
55		reg = <0x56000000 0x2000000>;
56		zephyr,memory-region = "XIP2";
57	};
58
59	soc {
60		compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
61
62		flash: flash-controller@c000 {
63			compatible = "ambiq,flash-controller";
64			reg = <0x0000c000 0x1f4000>;
65
66			#address-cells = <1>;
67			#size-cells = <1>;
68
69			/* Flash region */
70			flash0: flash@c000 {
71				compatible = "soc-nv-flash";
72				reg = <0x0000c000 0x1f4000>;
73			};
74		};
75
76		pwrcfg: pwrcfg@40021000 {
77			compatible = "ambiq,pwrctrl";
78			reg = <0x40021000 0x400>;
79			#pwrcfg-cells = <2>;
80		};
81
82		stimer0: stimer@40008140 {
83			compatible = "ambiq,stimer";
84			reg = <0x40008140 0x80>;
85			interrupts = <23 0>;
86			status = "okay";
87		};
88
89		counter0: counter@40008000 {
90			compatible = "ambiq,counter";
91			reg = <0x40008000 0x20>;
92			interrupts = <14 0>;
93			clock-frequency = <DT_FREQ_M(3)>;
94			clk-source = <2>;
95			status = "disabled";
96		};
97
98		counter1: counter@40008020 {
99			compatible = "ambiq,counter";
100			reg = <0x40008020 0x20>;
101			interrupts = <14 0>;
102			clock-frequency = <DT_FREQ_M(3)>;
103			clk-source = <2>;
104			status = "disabled";
105		};
106
107		counter2: counter@40008040 {
108			compatible = "ambiq,counter";
109			reg = <0x40008040 0x20>;
110			interrupts = <14 0>;
111			clock-frequency = <DT_FREQ_M(3)>;
112			clk-source = <2>;
113			status = "disabled";
114		};
115
116		counter3: counter@40008060 {
117			compatible = "ambiq,counter";
118			reg = <0x40008060 0x20>;
119			interrupts = <14 0>;
120			clock-frequency = <DT_FREQ_M(3)>;
121			clk-source = <2>;
122			status = "disabled";
123		};
124
125		counter4: counter@40008080 {
126			compatible = "ambiq,counter";
127			reg = <0x40008080 0x20>;
128			interrupts = <14 0>;
129			clock-frequency = <DT_FREQ_M(3)>;
130			clk-source = <2>;
131			status = "disabled";
132		};
133
134		counter5: counter@400080a0 {
135			compatible = "ambiq,counter";
136			reg = <0x400080A0 0x20>;
137			interrupts = <14 0>;
138			clock-frequency = <DT_FREQ_M(3)>;
139			clk-source = <2>;
140			status = "disabled";
141		};
142
143		counter6: counter@400080c0 {
144			compatible = "ambiq,counter";
145			reg = <0x400080C0 0x20>;
146			interrupts = <14 0>;
147			clock-frequency = <DT_FREQ_M(3)>;
148			clk-source = <2>;
149			status = "disabled";
150		};
151
152		counter7: counter@400080e0 {
153			compatible = "ambiq,counter";
154			reg = <0x400080E0 0x20>;
155			interrupts = <14 0>;
156			clock-frequency = <DT_FREQ_M(3)>;
157			clk-source = <2>;
158			status = "disabled";
159		};
160
161		uart0: uart@4001c000 {
162			compatible = "ambiq,uart", "arm,pl011";
163			reg = <0x4001c000 0x1000>;
164			interrupts = <15 0>;
165			interrupt-names = "UART0";
166			status = "disabled";
167			clocks = <&uartclk>;
168			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
169		};
170
171		uart1: uart@4001d000 {
172			compatible = "ambiq,uart", "arm,pl011";
173			reg = <0x4001d000 0x1000>;
174			interrupts = <16 0>;
175			interrupt-names = "UART1";
176			status = "disabled";
177			clocks = <&uartclk>;
178			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
179		};
180
181		spi0: spi@50004000 {
182			reg = <0x50004000 0x1000>;
183			#address-cells = <1>;
184			#size-cells = <0>;
185			interrupts = <6 0>;
186			status = "disabled";
187			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
188		};
189
190		spi1: spi@50005000 {
191			reg = <0x50005000 0x1000>;
192			#address-cells = <1>;
193			#size-cells = <0>;
194			interrupts = <7 0>;
195			status = "disabled";
196			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
197		};
198
199		spi2: spi@50006000 {
200			reg = <0x50006000 0x1000>;
201			#address-cells = <1>;
202			#size-cells = <0>;
203			interrupts = <8 0>;
204			status = "disabled";
205			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
206		};
207
208		spi3: spi@50007000 {
209			reg = <0x50007000 0x1000>;
210			#address-cells = <1>;
211			#size-cells = <0>;
212			interrupts = <9 0>;
213			status = "disabled";
214			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
215		};
216
217		spi4: spi@50008000 {
218			reg = <0x50008000 0x1000>;
219			#address-cells = <1>;
220			#size-cells = <0>;
221			interrupts = <10 0>;
222			status = "disabled";
223			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
224		};
225
226		spi5: spi@50009000 {
227			reg = <0x50009000 0x1000>;
228			#address-cells = <1>;
229			#size-cells = <0>;
230			interrupts = <11 0>;
231			status = "disabled";
232			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
233		};
234
235		i2c0: i2c@50004000 {
236			reg = <0x50004000 0x1000>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			interrupts = <6 0>;
240			status = "disabled";
241			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
242		};
243
244		i2c1: i2c@50005000 {
245			reg = <0x50005000 0x1000>;
246			#address-cells = <1>;
247			#size-cells = <0>;
248			interrupts = <7 0>;
249			status = "disabled";
250			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
251		};
252
253		i2c2: i2c@50006000 {
254			reg = <0x50006000 0x1000>;
255			#address-cells = <1>;
256			#size-cells = <0>;
257			interrupts = <8 0>;
258			status = "disabled";
259			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
260		};
261
262		i2c3: i2c@50007000 {
263			reg = <0x50007000 0x1000>;
264			#address-cells = <1>;
265			#size-cells = <0>;
266			interrupts = <9 0>;
267			status = "disabled";
268			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
269		};
270
271		i2c4: i2c@50008000 {
272			reg = <0x50008000 0x1000>;
273			#address-cells = <1>;
274			#size-cells = <0>;
275			interrupts = <10 0>;
276			status = "disabled";
277			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
278		};
279
280		i2c5: i2c@50009000 {
281			reg = <0x50009000 0x1000>;
282			#address-cells = <1>;
283			#size-cells = <0>;
284			interrupts = <11 0>;
285			status = "disabled";
286			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
287		};
288
289		mspi0: mspi@50014000 {
290			compatible = "ambiq,mspi-controller";
291			reg = <0x50014000 0x400>,<0x52000000 0x2000000>;
292			clock-frequency = <48000000>;
293			interrupts = <20 0>;
294			#address-cells = <1>;
295			#size-cells = <0>;
296			status = "disabled";
297			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
298		};
299
300		mspi1: mspi@50015000 {
301			compatible = "ambiq,mspi-controller";
302			reg = <0x50015000 0x400>,<0x54000000 0x2000000>;
303			clock-frequency = <48000000>;
304			interrupts = <32 0>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307			status = "disabled";
308			ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
309		};
310
311		mspi2: mspi@50016000 {
312			compatible = "ambiq,mspi-controller";
313			clock-frequency = <48000000>;
314			reg = <0x50016000 0x400>,<0x56000000 0x2000000>;
315			interrupts = <33 0>;
316			#address-cells = <1>;
317			#size-cells = <0>;
318			status = "disabled";
319			ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
320		};
321
322		bleif: spi@5000c000 {
323			compatible = "ambiq,spi-bleif";
324			reg = <0x5000c000 0x414>;
325			interrupts = <12 1>;
326			#address-cells = <1>;
327			#size-cells = <0>;
328			status = "disabled";
329			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
330
331			bt_hci_apollo: bt-hci@0 {
332				compatible = "ambiq,bt-hci-spi";
333				spi-max-frequency = <DT_FREQ_M(6)>;
334				reg = <0>;
335			};
336		};
337
338		pinctrl: pin-controller@40010000 {
339			compatible = "ambiq,apollo3-pinctrl";
340			reg = <0x40010000 0x800>;
341			#address-cells = <1>;
342			#size-cells = <0>;
343
344			gpio: gpio@40010000 {
345				compatible = "ambiq,gpio";
346				gpio-map-mask = <0xffffffe0 0xffffffc0>;
347				gpio-map-pass-thru = <0x1f 0x3f>;
348				gpio-map = <
349					0x00 0x0 &gpio0_31 0x0 0x0
350					0x20 0x0 &gpio32_63 0x0 0x0
351					0x40 0x0 &gpio64_95 0x0 0x0
352				>;
353				reg = <0x40010000>;
354				#gpio-cells = <2>;
355				#address-cells = <1>;
356				#size-cells = <0>;
357				ranges;
358
359				gpio0_31: gpio0_31@0 {
360					compatible = "ambiq,gpio-bank";
361					gpio-controller;
362					#gpio-cells = <2>;
363					reg = <0>;
364					interrupts = <13 0>;
365					status = "disabled";
366				};
367
368				gpio32_63: gpio32_63@20 {
369					compatible = "ambiq,gpio-bank";
370					gpio-controller;
371					#gpio-cells = <2>;
372					reg = <0x20>;
373					interrupts = <13 0>;
374					status = "disabled";
375				};
376
377				gpio64_95: gpio64_95@40 {
378					compatible = "ambiq,gpio-bank";
379					gpio-controller;
380					#gpio-cells = <2>;
381					reg = <0x40>;
382					interrupts = <13 0>;
383					status = "disabled";
384					ngpios = <10>;
385				};
386			};
387		};
388
389		wdt0: watchdog@40024000 {
390			compatible = "ambiq,watchdog";
391			reg = <0x40024000 0x400>;
392			interrupts = <1 0>;
393			clock-frequency = <16>;
394			status = "disabled";
395		};
396	};
397};
398
399&nvic {
400	arm,num-irq-priority-bits = <3>;
401};
402