1/*
2 * Copyright (c) 2023, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8
9#include <zephyr/dt-bindings/i2c/i2c.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "snps,archs4xd";
20			reg = <0>;
21		};
22
23		cpu@1 {
24			device_type = "cpu";
25			compatible = "snps,archs4xd";
26			reg = <1>;
27		};
28
29		cpu@2 {
30			device_type = "cpu";
31			compatible = "snps,archs4xd";
32			reg = <2>;
33		};
34
35		cpu@3 {
36			device_type = "cpu";
37			compatible = "snps,archs4xd";
38			reg = <3>;
39		};
40
41	};
42
43	intc: arcv2-intc {
44		compatible = "snps,arcv2-intc";
45		interrupt-controller;
46		#interrupt-cells = <2>;
47	};
48
49
50	idu_intc: idu-interrupt-controller {
51		compatible = "snps,archs-idu-intc";
52		interrupt-controller;
53		#interrupt-cells = <2>;
54		interrupt-parent = <&intc>;
55	};
56
57	ici: intercore-interrupt-unit {
58		compatible = "snps,archs-ici";
59		interrupts = <19 1>;
60		interrupt-parent = <&intc>;
61	};
62
63	timer0: timer0 {
64		compatible = "snps,arc-timer";
65		interrupts = <16 1>;
66		interrupt-parent = <&intc>;
67	};
68
69	timer1: timer1 {
70		compatible = "snps,arc-timer";
71		interrupts = <17 1>;
72		interrupt-parent = <&intc>;
73	};
74
75	soc {
76		#address-cells = <1>;
77		#size-cells = <1>;
78		compatible = "simple-bus";
79		interrupt-parent = <&idu_intc>;
80		ranges;
81
82		ddr0: memory@90000000 {
83			device_type = "memory";
84			reg = <0x90000000 0x50000000>;
85		};
86
87		uart_dbg: uart@f0005000 {
88			compatible = "ns16550";
89			clock-frequency = <33333333>;
90			reg = <0xf0005000 0x1000>;
91			interrupts = <30 1>;
92			reg-shift = <2>;
93		};
94
95		uart0: uart@f0026000 {
96			compatible = "ns16550";
97			clock-frequency = <33333333>;
98			reg = <0xf0026000 0x100>;
99			interrupts = <46 1>;
100			reg-shift = <2>;
101			status = "disabled";
102		};
103
104		uart1: uart@f0027000{
105			compatible = "ns16550";
106			clock-frequency = <33333333>;
107			reg = <0xf0027000 0x100>;
108			interrupts = <47 1>;
109			reg-shift = <2>;
110			status = "disabled";
111		};
112
113		uart2: uart@f0028000 {
114			compatible = "ns16550";
115			clock-frequency = <33333333>;
116			reg = <0xf0028000 0x100>;
117			interrupts = <48 1>;
118			reg-shift = <2>;
119			status = "disabled";
120		};
121
122		gpio0: gpio@f0003000 {
123			compatible = "snps,designware-gpio";
124			reg = <0xf0003000 0x80>;
125			ngpios = <24>;
126			interrupt-parent = <&idu_intc>;
127
128			gpio-controller;
129			#gpio-cells = <2>;
130
131			status = "disabled";
132		};
133
134		creg_gpio: creg_gpio@f00014b0 {
135			compatible = "snps,creg-gpio";
136			reg = <0xf00014b0 0x4>;
137			ngpios = <12>;
138			bit_per_gpio = <2>;
139			off_val = <0>;
140			on_val = <2>;
141
142			gpio-controller;
143			#gpio-cells = <2>;
144
145			status = "disabled";
146		};
147
148		i2c0: i2c@f0023000 {
149			compatible = "snps,designware-i2c";
150			clock-frequency = <I2C_BITRATE_STANDARD>;
151			#address-cells = <1>;
152			#size-cells = <0>;
153			reg = <0xf0023000 0x100>;
154			interrupts = <43 1>;
155
156			status = "disabled";
157		};
158
159		i2c1: i2c@f0024000 {
160			compatible = "snps,designware-i2c";
161			clock-frequency = <I2C_BITRATE_STANDARD>;
162			#address-cells = <1>;
163			#size-cells = <0>;
164			reg = <0xf0024000 0x100>;
165			interrupts = <44 1>;
166
167			status = "disabled";
168		};
169
170		i2c2: i2c@f0025000 {
171			compatible = "snps,designware-i2c";
172			clock-frequency = <I2C_BITRATE_STANDARD>;
173			#address-cells = <1>;
174			#size-cells = <0>;
175			reg = <0xf0025000 0x100>;
176			interrupts = <45 1>;
177
178			status = "disabled";
179		};
180
181		spi0: spi@f0020000 {
182			compatible = "snps,designware-spi";
183			#address-cells = <1>;
184			#size-cells = <0>;
185			reg = <0xf0020000 0x100>;
186			interrupts = <40 1>;
187			fifo-depth = <32>;
188			max-xfer-size = <16>;
189			status = "disabled";
190		};
191
192		spi1: spi@f0021000 {
193			compatible = "snps,designware-spi";
194			#address-cells = <1>;
195			#size-cells = <0>;
196			reg = <0xf0021000 0x100>;
197			interrupts = <41 1>;
198			fifo-depth = <32>;
199			max-xfer-size = <16>;
200			status = "disabled";
201		};
202
203		spi2: spi@f0022000 {
204			compatible = "snps,designware-spi";
205			#address-cells = <1>;
206			#size-cells = <0>;
207			reg = <0xf0022000 0x100>;
208			interrupts = <42 1>;
209			fifo-depth = <32>;
210			max-xfer-size = <16>;
211			status = "disabled";
212		};
213	};
214};
215