1 /* Copyright (C) 2023 BeagleBoard.org Foundation
2 * Copyright (C) 2023 S Prashanth
3 * Copyright (c) 2024 Texas Instruments Incorporated
4 * Andrew Davis <afd@ti.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/timer/system_timer.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/sys_clock.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/spinlock.h>
15
16 #include <zephyr/drivers/timer/ti_dmtimer.h>
17
18 #define DT_DRV_COMPAT ti_am654_timer
19
20 #define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
21
22 #define TIMER_IRQ_NUM DT_INST_IRQN(0)
23 #define TIMER_IRQ_PRIO DT_INST_IRQ(0, priority)
24 #define TIMER_IRQ_FLAGS DT_INST_IRQ(0, flags)
25
26 #define CYC_PER_TICK ((uint32_t)(sys_clock_hw_cycles_per_sec() \
27 / CONFIG_SYS_CLOCK_TICKS_PER_SEC))
28
29 #define MAX_TICKS ((k_ticks_t)(UINT32_MAX / CYC_PER_TICK) - 1)
30
31 static struct k_spinlock lock;
32
33 static uint32_t last_cycle;
34
35 #define TI_DM_TIMER_READ(reg) sys_read32(TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg)
36
37 #define TI_DM_TIMER_MASK(reg) TI_DM_TIMER_ ## reg ## _MASK
38 #define TI_DM_TIMER_SHIFT(reg) TI_DM_TIMER_ ## reg ## _SHIFT
39 #define TI_DM_TIMER_WRITE(data, reg, bits) \
40 ti_dm_timer_write_masks(data, \
41 TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg, \
42 TI_DM_TIMER_MASK(reg ## _ ## bits), \
43 TI_DM_TIMER_SHIFT(reg ## _ ## bits))
44
ti_dm_timer_write_masks(uint32_t data,uint32_t reg,uint32_t mask,uint32_t shift)45 static void ti_dm_timer_write_masks(uint32_t data, uint32_t reg, uint32_t mask, uint32_t shift)
46 {
47 uint32_t reg_val;
48
49 reg_val = sys_read32(reg);
50 reg_val = (reg_val & ~(mask)) | (data << shift);
51 sys_write32(reg_val, reg);
52 }
53
ti_dmtimer_isr(void * data)54 static void ti_dmtimer_isr(void *data)
55 {
56 /* If no pending event */
57 if (!TI_DM_TIMER_READ(IRQSTATUS))
58 return;
59
60 k_spinlock_key_t key = k_spin_lock(&lock);
61
62 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
63 uint32_t delta_cycles = curr_cycle - last_cycle;
64 uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
65
66 last_cycle = curr_cycle;
67
68 /* ACK match interrupt */
69 TI_DM_TIMER_WRITE(1, IRQSTATUS, MAT_IT_FLAG);
70
71 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
72 /* Setup next match time */
73 uint64_t next_cycle = curr_cycle + CYC_PER_TICK;
74
75 TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
76 }
77
78 k_spin_unlock(&lock, key);
79
80 sys_clock_announce(delta_ticks);
81 }
82
sys_clock_set_timeout(int32_t ticks,bool idle)83 void sys_clock_set_timeout(int32_t ticks, bool idle)
84 {
85 ARG_UNUSED(idle);
86 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
87 /* Not supported on tickful kernels */
88 return;
89 }
90
91 ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
92 ticks = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
93
94 k_spinlock_key_t key = k_spin_lock(&lock);
95
96 /* Setup next match time */
97 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
98 uint32_t next_cycle = curr_cycle + (ticks * CYC_PER_TICK);
99
100 TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
101
102 k_spin_unlock(&lock, key);
103 }
104
sys_clock_cycle_get_32(void)105 uint32_t sys_clock_cycle_get_32(void)
106 {
107 k_spinlock_key_t key = k_spin_lock(&lock);
108
109 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
110
111 k_spin_unlock(&lock, key);
112
113 return curr_cycle;
114 }
115
sys_clock_elapsed(void)116 unsigned int sys_clock_elapsed(void)
117 {
118 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
119 /* Always return 0 for tickful kernel system */
120 return 0;
121 }
122
123 k_spinlock_key_t key = k_spin_lock(&lock);
124
125 uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
126 uint32_t delta_cycles = curr_cycle - last_cycle;
127 uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
128
129 k_spin_unlock(&lock, key);
130
131 return delta_ticks;
132 }
133
sys_clock_driver_init(void)134 static int sys_clock_driver_init(void)
135 {
136 last_cycle = 0;
137
138 IRQ_CONNECT(TIMER_IRQ_NUM, TIMER_IRQ_PRIO, ti_dmtimer_isr, NULL, TIMER_IRQ_FLAGS);
139
140 /* Select autoreload mode */
141 TI_DM_TIMER_WRITE(1, TCLR, AR);
142
143 /* Enable match interrupt */
144 TI_DM_TIMER_WRITE(1, IRQENABLE_SET, MAT_EN_FLAG);
145
146 /* Load timer counter value */
147 TI_DM_TIMER_WRITE(0, TCRR, TIMER_COUNTER);
148
149 /* Load timer load value */
150 TI_DM_TIMER_WRITE(0, TLDR, LOAD_VALUE);
151
152 /* Load timer compare value */
153 TI_DM_TIMER_WRITE(CYC_PER_TICK, TMAR, COMPARE_VALUE);
154
155 /* Enable compare mode */
156 TI_DM_TIMER_WRITE(1, TCLR, CE);
157
158 /* Start the timer */
159 TI_DM_TIMER_WRITE(1, TCLR, ST);
160
161 irq_enable(TIMER_IRQ_NUM);
162
163 return 0;
164 }
165
166 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
167 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
168
