1 /*
2 * Copyright (c) 2019 Mohamed ElShahawi (extremegtx@hotmail.com)
3 * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT espressif_esp32_uart
9
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
11 /* TODO: include w/o prefix */
12 #ifdef CONFIG_SOC_SERIES_ESP32
13 #include <esp32/rom/ets_sys.h>
14 #include <esp32/rom/gpio.h>
15 #include <soc/dport_reg.h>
16 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
17 #include <esp32s2/rom/ets_sys.h>
18 #include <esp32s2/rom/gpio.h>
19 #include <soc/dport_reg.h>
20 #elif defined(CONFIG_SOC_SERIES_ESP32S3)
21 #include <esp32s3/rom/ets_sys.h>
22 #include <esp32s3/rom/gpio.h>
23 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
24 #elif defined(CONFIG_SOC_SERIES_ESP32C3)
25 #include <esp32c3/rom/ets_sys.h>
26 #include <esp32c3/rom/gpio.h>
27 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
28 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
29 #include <esp32c6/rom/ets_sys.h>
30 #include <esp32c6/rom/gpio.h>
31 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
32 #endif
33 #ifdef CONFIG_UART_ASYNC_API
34 #include <zephyr/drivers/dma.h>
35 #include <zephyr/drivers/dma/dma_esp32.h>
36 #include <hal/uhci_ll.h>
37 #endif
38 #include <soc/uart_struct.h>
39 #include <hal/uart_ll.h>
40 #include <hal/uart_hal.h>
41 #include <hal/uart_types.h>
42 #include <esp_clk_tree.h>
43 #include <zephyr/drivers/pinctrl.h>
44
45 #include <soc/uart_reg.h>
46 #include <zephyr/device.h>
47 #include <soc.h>
48 #include <zephyr/drivers/uart.h>
49
50 #if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
51 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
52 #else
53 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
54 #endif
55
56 #include <zephyr/drivers/clock_control.h>
57 #include <errno.h>
58 #include <zephyr/sys/util.h>
59 #include <esp_attr.h>
60 #include <zephyr/logging/log.h>
61
62 LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL);
63
64 #if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
65 #define ISR_HANDLER isr_handler_t
66 #else
67 #define ISR_HANDLER intr_handler_t
68 #endif
69
70 struct uart_esp32_config {
71 const struct device *clock_dev;
72 const struct pinctrl_dev_config *pcfg;
73 const clock_control_subsys_t clock_subsys;
74 int irq_source;
75 int irq_priority;
76 bool tx_invert;
77 bool rx_invert;
78 #if CONFIG_UART_ASYNC_API
79 const struct device *dma_dev;
80 uint8_t tx_dma_channel;
81 uint8_t rx_dma_channel;
82 #endif
83 };
84
85 #if CONFIG_UART_ASYNC_API
86 struct uart_esp32_async_data {
87 struct k_work_delayable tx_timeout_work;
88 const uint8_t *tx_buf;
89 size_t tx_len;
90 struct k_work_delayable rx_timeout_work;
91 uint8_t *rx_buf;
92 uint8_t *rx_next_buf;
93 size_t rx_len;
94 size_t rx_next_len;
95 size_t rx_timeout;
96 volatile size_t rx_counter;
97 size_t rx_offset;
98 uart_callback_t cb;
99 void *user_data;
100 };
101 #endif
102
103 /* driver data */
104 struct uart_esp32_data {
105 struct uart_config uart_config;
106 uart_hal_context_t hal;
107 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
108 uart_irq_callback_user_data_t irq_cb;
109 void *irq_cb_data;
110 #endif
111 #if CONFIG_UART_ASYNC_API
112 struct uart_esp32_async_data async;
113 uhci_dev_t *uhci_dev;
114 const struct device *uart_dev;
115 #endif
116 };
117
118 #define UART_FIFO_LIMIT (UART_LL_FIFO_DEF_LEN)
119 #define UART_TX_FIFO_THRESH (CONFIG_UART_ESP32_TX_FIFO_THRESH)
120 #define UART_RX_FIFO_THRESH (CONFIG_UART_ESP32_RX_FIFO_THRESH)
121
122 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
123 static void uart_esp32_isr(void *arg);
124 #endif
125
uart_esp32_poll_in(const struct device * dev,unsigned char * p_char)126 static int uart_esp32_poll_in(const struct device *dev, unsigned char *p_char)
127 {
128 struct uart_esp32_data *data = dev->data;
129 int inout_rd_len = 1;
130
131 if (uart_hal_get_rxfifo_len(&data->hal) == 0) {
132 return -1;
133 }
134
135 uart_hal_read_rxfifo(&data->hal, p_char, &inout_rd_len);
136
137 return 0;
138 }
139
uart_esp32_poll_out(const struct device * dev,unsigned char c)140 static void uart_esp32_poll_out(const struct device *dev, unsigned char c)
141 {
142 struct uart_esp32_data *data = dev->data;
143 uint32_t written;
144
145 /* Wait for space in FIFO */
146 while (uart_hal_get_txfifo_len(&data->hal) == 0) {
147 ; /* Wait */
148 }
149
150 /* Send a character */
151 uart_hal_write_txfifo(&data->hal, &c, 1, &written);
152 }
153
uart_esp32_err_check(const struct device * dev)154 static int uart_esp32_err_check(const struct device *dev)
155 {
156 struct uart_esp32_data *data = dev->data;
157 uint32_t mask = uart_hal_get_intsts_mask(&data->hal);
158 uint32_t err = mask & (UART_INTR_PARITY_ERR | UART_INTR_FRAM_ERR);
159
160 return err;
161 }
162
163 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
uart_esp32_config_get(const struct device * dev,struct uart_config * cfg)164 static int uart_esp32_config_get(const struct device *dev, struct uart_config *cfg)
165 {
166 struct uart_esp32_data *data = dev->data;
167 uart_parity_t parity;
168 uart_stop_bits_t stop_bit;
169 uart_word_length_t data_bit;
170 uart_hw_flowcontrol_t hw_flow;
171 uart_sclk_t src_clk;
172 uint32_t sclk_freq;
173
174 uart_hal_get_sclk(&data->hal, &src_clk);
175 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk,
176 ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
177 uart_hal_get_baudrate(&data->hal, &cfg->baudrate, sclk_freq);
178
179 uart_hal_get_parity(&data->hal, &parity);
180 switch (parity) {
181 case UART_PARITY_DISABLE:
182 cfg->parity = UART_CFG_PARITY_NONE;
183 break;
184 case UART_PARITY_EVEN:
185 cfg->parity = UART_CFG_PARITY_EVEN;
186 break;
187 case UART_PARITY_ODD:
188 cfg->parity = UART_CFG_PARITY_ODD;
189 break;
190 default:
191 return -ENOTSUP;
192 }
193
194 uart_hal_get_stop_bits(&data->hal, &stop_bit);
195 switch (stop_bit) {
196 case UART_STOP_BITS_1:
197 cfg->stop_bits = UART_CFG_STOP_BITS_1;
198 break;
199 case UART_STOP_BITS_1_5:
200 cfg->stop_bits = UART_CFG_STOP_BITS_1_5;
201 break;
202 case UART_STOP_BITS_2:
203 cfg->stop_bits = UART_CFG_STOP_BITS_2;
204 break;
205 default:
206 return -ENOTSUP;
207 }
208
209 uart_hal_get_data_bit_num(&data->hal, &data_bit);
210 switch (data_bit) {
211 case UART_DATA_5_BITS:
212 cfg->data_bits = UART_CFG_DATA_BITS_5;
213 break;
214 case UART_DATA_6_BITS:
215 cfg->data_bits = UART_CFG_DATA_BITS_6;
216 break;
217 case UART_DATA_7_BITS:
218 cfg->data_bits = UART_CFG_DATA_BITS_7;
219 break;
220 case UART_DATA_8_BITS:
221 cfg->data_bits = UART_CFG_DATA_BITS_8;
222 break;
223 default:
224 return -ENOTSUP;
225 }
226
227 uart_hal_get_hw_flow_ctrl(&data->hal, &hw_flow);
228 switch (hw_flow) {
229 case UART_HW_FLOWCTRL_DISABLE:
230 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
231 break;
232 case UART_HW_FLOWCTRL_CTS_RTS:
233 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS;
234 break;
235 default:
236 return -ENOTSUP;
237 }
238
239 if (uart_hal_is_mode_rs485_half_duplex(&data->hal)) {
240 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RS485;
241 }
242
243 return 0;
244 }
245 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
246
uart_esp32_configure(const struct device * dev,const struct uart_config * cfg)247 static int uart_esp32_configure(const struct device *dev, const struct uart_config *cfg)
248 {
249 const struct uart_esp32_config *config = dev->config;
250 struct uart_esp32_data *data = dev->data;
251 uart_sclk_t src_clk;
252 uint32_t sclk_freq;
253
254 int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
255
256 if (ret < 0) {
257 return ret;
258 }
259
260 if (!device_is_ready(config->clock_dev)) {
261 return -ENODEV;
262 }
263
264 clock_control_on(config->clock_dev, config->clock_subsys);
265
266 uart_hal_set_sclk(&data->hal, UART_SCLK_DEFAULT);
267 uart_hal_set_rxfifo_full_thr(&data->hal, UART_RX_FIFO_THRESH);
268 uart_hal_set_txfifo_empty_thr(&data->hal, UART_TX_FIFO_THRESH);
269 uart_hal_rxfifo_rst(&data->hal);
270
271 switch (cfg->parity) {
272 case UART_CFG_PARITY_NONE:
273 uart_hal_set_parity(&data->hal, UART_PARITY_DISABLE);
274 break;
275 case UART_CFG_PARITY_EVEN:
276 uart_hal_set_parity(&data->hal, UART_PARITY_EVEN);
277 break;
278 case UART_CFG_PARITY_ODD:
279 uart_hal_set_parity(&data->hal, UART_PARITY_ODD);
280 break;
281 default:
282 return -ENOTSUP;
283 }
284
285 switch (cfg->stop_bits) {
286 case UART_CFG_STOP_BITS_1:
287 uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_1);
288 break;
289 case UART_CFG_STOP_BITS_1_5:
290 uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_1_5);
291 break;
292 case UART_CFG_STOP_BITS_2:
293 uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_2);
294 break;
295 default:
296 return -ENOTSUP;
297 }
298
299 switch (cfg->data_bits) {
300 case UART_CFG_DATA_BITS_5:
301 uart_hal_set_data_bit_num(&data->hal, UART_DATA_5_BITS);
302 break;
303 case UART_CFG_DATA_BITS_6:
304 uart_hal_set_data_bit_num(&data->hal, UART_DATA_6_BITS);
305 break;
306 case UART_CFG_DATA_BITS_7:
307 uart_hal_set_data_bit_num(&data->hal, UART_DATA_7_BITS);
308 break;
309 case UART_CFG_DATA_BITS_8:
310 uart_hal_set_data_bit_num(&data->hal, UART_DATA_8_BITS);
311 break;
312 default:
313 return -ENOTSUP;
314 }
315
316 uart_hal_set_mode(&data->hal, UART_MODE_UART);
317
318 switch (cfg->flow_ctrl) {
319 case UART_CFG_FLOW_CTRL_NONE:
320 uart_hal_set_hw_flow_ctrl(&data->hal, UART_HW_FLOWCTRL_DISABLE, 0);
321 break;
322 case UART_CFG_FLOW_CTRL_RTS_CTS:
323 uart_hal_set_hw_flow_ctrl(&data->hal, UART_HW_FLOWCTRL_CTS_RTS, 10);
324 break;
325 case UART_CFG_FLOW_CTRL_RS485:
326 uart_hal_set_mode(&data->hal, UART_MODE_RS485_HALF_DUPLEX);
327 break;
328 default:
329 return -ENOTSUP;
330 }
331
332 uart_hal_get_sclk(&data->hal, &src_clk);
333 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk,
334 ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
335 uart_hal_set_baudrate(&data->hal, cfg->baudrate, sclk_freq);
336
337 uart_hal_set_rx_timeout(&data->hal, 0x16);
338
339 if (config->tx_invert) {
340 uart_hal_inverse_signal(&data->hal, UART_SIGNAL_TXD_INV);
341 }
342
343 if (config->rx_invert) {
344 uart_hal_inverse_signal(&data->hal, UART_SIGNAL_RXD_INV);
345 }
346 return 0;
347 }
348
349 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
350
uart_esp32_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)351 static int uart_esp32_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
352 {
353 struct uart_esp32_data *data = dev->data;
354 uint32_t written = 0;
355
356 if (len < 0) {
357 return 0;
358 }
359
360 uart_hal_write_txfifo(&data->hal, tx_data, len, &written);
361 return written;
362 }
363
uart_esp32_fifo_read(const struct device * dev,uint8_t * rx_data,const int len)364 static int uart_esp32_fifo_read(const struct device *dev, uint8_t *rx_data, const int len)
365 {
366 struct uart_esp32_data *data = dev->data;
367 const int num_rx = uart_hal_get_rxfifo_len(&data->hal);
368 int read = MIN(len, num_rx);
369
370 if (!read) {
371 return 0;
372 }
373
374 uart_hal_read_rxfifo(&data->hal, rx_data, &read);
375 return read;
376 }
377
uart_esp32_irq_tx_enable(const struct device * dev)378 static void uart_esp32_irq_tx_enable(const struct device *dev)
379 {
380 struct uart_esp32_data *data = dev->data;
381
382 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
383 uart_hal_ena_intr_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
384 }
385
uart_esp32_irq_tx_disable(const struct device * dev)386 static void uart_esp32_irq_tx_disable(const struct device *dev)
387 {
388 struct uart_esp32_data *data = dev->data;
389
390 uart_hal_disable_intr_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
391 }
392
uart_esp32_irq_tx_ready(const struct device * dev)393 static int uart_esp32_irq_tx_ready(const struct device *dev)
394 {
395 struct uart_esp32_data *data = dev->data;
396
397 return (uart_hal_get_txfifo_len(&data->hal) > 0 &&
398 uart_hal_get_intr_ena_status(&data->hal) & UART_INTR_TXFIFO_EMPTY);
399 }
400
uart_esp32_irq_rx_disable(const struct device * dev)401 static void uart_esp32_irq_rx_disable(const struct device *dev)
402 {
403 struct uart_esp32_data *data = dev->data;
404
405 uart_hal_disable_intr_mask(&data->hal, UART_INTR_RXFIFO_FULL);
406 uart_hal_disable_intr_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
407 }
408
uart_esp32_irq_tx_complete(const struct device * dev)409 static int uart_esp32_irq_tx_complete(const struct device *dev)
410 {
411 struct uart_esp32_data *data = dev->data;
412
413 return uart_hal_is_tx_idle(&data->hal);
414 }
415
uart_esp32_irq_rx_ready(const struct device * dev)416 static int uart_esp32_irq_rx_ready(const struct device *dev)
417 {
418 struct uart_esp32_data *data = dev->data;
419
420 return (uart_hal_get_rxfifo_len(&data->hal) > 0);
421 }
422
uart_esp32_irq_err_enable(const struct device * dev)423 static void uart_esp32_irq_err_enable(const struct device *dev)
424 {
425 struct uart_esp32_data *data = dev->data;
426
427 /* enable framing, parity */
428 uart_hal_ena_intr_mask(&data->hal, UART_INTR_FRAM_ERR);
429 uart_hal_ena_intr_mask(&data->hal, UART_INTR_PARITY_ERR);
430 }
431
uart_esp32_irq_err_disable(const struct device * dev)432 static void uart_esp32_irq_err_disable(const struct device *dev)
433 {
434 struct uart_esp32_data *data = dev->data;
435
436 uart_hal_disable_intr_mask(&data->hal, UART_INTR_FRAM_ERR);
437 uart_hal_disable_intr_mask(&data->hal, UART_INTR_PARITY_ERR);
438 }
439
uart_esp32_irq_is_pending(const struct device * dev)440 static int uart_esp32_irq_is_pending(const struct device *dev)
441 {
442 return uart_esp32_irq_rx_ready(dev) || uart_esp32_irq_tx_ready(dev);
443 }
444
uart_esp32_irq_update(const struct device * dev)445 static int uart_esp32_irq_update(const struct device *dev)
446 {
447 struct uart_esp32_data *data = dev->data;
448
449 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_FULL);
450 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
451 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
452
453 return 1;
454 }
455
uart_esp32_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)456 static void uart_esp32_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
457 void *cb_data)
458 {
459 struct uart_esp32_data *data = dev->data;
460
461 data->irq_cb = cb;
462 data->irq_cb_data = cb_data;
463
464 #if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
465 data->async.cb = NULL;
466 data->async.user_data = NULL;
467 #endif
468 }
469
470 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
471
472 #ifdef CONFIG_UART_ASYNC_API
473
uart_esp32_async_timer_start(struct k_work_delayable * work,size_t timeout)474 static inline void uart_esp32_async_timer_start(struct k_work_delayable *work, size_t timeout)
475 {
476 if ((timeout != SYS_FOREVER_US) && (timeout != 0)) {
477 LOG_DBG("Async timer started for %d us", timeout);
478 k_work_reschedule(work, K_USEC(timeout));
479 }
480 }
481
482 #endif
483 #if CONFIG_UART_ASYNC_API || CONFIG_UART_INTERRUPT_DRIVEN
484
uart_esp32_irq_rx_enable(const struct device * dev)485 static void uart_esp32_irq_rx_enable(const struct device *dev)
486 {
487 struct uart_esp32_data *data = dev->data;
488
489 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_FULL);
490 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
491 uart_hal_ena_intr_mask(&data->hal, UART_INTR_RXFIFO_FULL);
492 uart_hal_ena_intr_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
493 }
494
uart_esp32_isr(void * arg)495 static void uart_esp32_isr(void *arg)
496 {
497 const struct device *dev = (const struct device *)arg;
498 struct uart_esp32_data *data = dev->data;
499 uint32_t uart_intr_status = uart_hal_get_intsts_mask(&data->hal);
500 const struct uart_esp32_config *config = dev->config;
501
502 if (uart_intr_status == 0) {
503 return;
504 }
505 uart_hal_clr_intsts_mask(&data->hal, uart_intr_status);
506
507 #if CONFIG_UART_INTERRUPT_DRIVEN
508 /* Verify if the callback has been registered */
509 if (data->irq_cb) {
510 data->irq_cb(dev, data->irq_cb_data);
511 }
512 #endif
513
514 #if CONFIG_UART_ASYNC_API
515 if (uart_intr_status & UART_INTR_RXFIFO_FULL) {
516 data->async.rx_counter++;
517 uart_esp32_async_timer_start(&data->async.rx_timeout_work, data->async.rx_timeout);
518 }
519 #endif
520 }
521
522 #endif
523
524 #if CONFIG_UART_ASYNC_API
uart_esp32_dma_rx_done(const struct device * dma_dev,void * user_data,uint32_t channel,int status)525 static void IRAM_ATTR uart_esp32_dma_rx_done(const struct device *dma_dev, void *user_data,
526 uint32_t channel, int status)
527 {
528 const struct device *uart_dev = user_data;
529 const struct uart_esp32_config *config = uart_dev->config;
530 struct uart_esp32_data *data = uart_dev->data;
531 struct uart_event evt = {0};
532 struct dma_status dma_status = {0};
533 unsigned int key = irq_lock();
534
535 /* If the receive buffer is not complete we reload the DMA at current buffer position and
536 * let the timeout callback handle the notifications
537 */
538 if (data->async.rx_counter != data->async.rx_len) {
539 dma_reload(config->dma_dev, config->rx_dma_channel, 0,
540 (uint32_t)data->async.rx_buf + data->async.rx_counter,
541 data->async.rx_len - data->async.rx_counter);
542 dma_start(config->dma_dev, config->rx_dma_channel);
543 data->uhci_dev->pkt_thres.thrs = data->async.rx_len - data->async.rx_counter;
544 irq_unlock(key);
545 return;
546 }
547
548 /*Notify RX_RDY*/
549 evt.type = UART_RX_RDY;
550 evt.data.rx.buf = data->async.rx_buf;
551 evt.data.rx.len = data->async.rx_counter - data->async.rx_offset;
552 evt.data.rx.offset = data->async.rx_offset;
553
554 if (data->async.cb && evt.data.rx.len) {
555 data->async.cb(data->uart_dev, &evt, data->async.user_data);
556 }
557
558 data->async.rx_offset = 0;
559 data->async.rx_counter = 0;
560
561 /*Release current buffer*/
562 evt.type = UART_RX_BUF_RELEASED;
563 evt.data.rx_buf.buf = data->async.rx_buf;
564 if (data->async.cb) {
565 data->async.cb(uart_dev, &evt, data->async.user_data);
566 }
567
568 /*Load next buffer and request another*/
569 data->async.rx_buf = data->async.rx_next_buf;
570 data->async.rx_len = data->async.rx_next_len;
571 data->async.rx_next_buf = NULL;
572 data->async.rx_next_len = 0U;
573 evt.type = UART_RX_BUF_REQUEST;
574 if (data->async.cb) {
575 data->async.cb(uart_dev, &evt, data->async.user_data);
576 }
577
578 /*Notify RX_DISABLED when there is no buffer*/
579 if (!data->async.rx_buf) {
580 evt.type = UART_RX_DISABLED;
581 if (data->async.cb) {
582 data->async.cb(uart_dev, &evt, data->async.user_data);
583 }
584 } else {
585 /*Reload DMA with new buffer*/
586 dma_reload(config->dma_dev, config->rx_dma_channel, 0, (uint32_t)data->async.rx_buf,
587 data->async.rx_len);
588 dma_start(config->dma_dev, config->rx_dma_channel);
589 data->uhci_dev->pkt_thres.thrs = data->async.rx_len;
590 }
591
592 irq_unlock(key);
593 }
594
uart_esp32_dma_tx_done(const struct device * dma_dev,void * user_data,uint32_t channel,int status)595 static void IRAM_ATTR uart_esp32_dma_tx_done(const struct device *dma_dev, void *user_data,
596 uint32_t channel, int status)
597 {
598 const struct device *uart_dev = user_data;
599 const struct uart_esp32_config *config = uart_dev->config;
600 struct uart_esp32_data *data = uart_dev->data;
601 struct uart_event evt = {0};
602 unsigned int key = irq_lock();
603
604 k_work_cancel_delayable(&data->async.tx_timeout_work);
605
606 evt.type = UART_TX_DONE;
607 evt.data.tx.buf = data->async.tx_buf;
608 evt.data.tx.len = data->async.tx_len;
609 if (data->async.cb) {
610 data->async.cb(uart_dev, &evt, data->async.user_data);
611 }
612
613 /* Reset TX Buffer */
614 data->async.tx_buf = NULL;
615 data->async.tx_len = 0U;
616 irq_unlock(key);
617 }
618
uart_esp32_async_tx_abort(const struct device * dev)619 static int uart_esp32_async_tx_abort(const struct device *dev)
620 {
621 const struct uart_esp32_config *config = dev->config;
622 struct uart_esp32_data *data = dev->data;
623 struct uart_event evt = {0};
624 int err = 0;
625 unsigned int key = irq_lock();
626
627 k_work_cancel_delayable(&data->async.tx_timeout_work);
628
629 err = dma_stop(config->dma_dev, config->tx_dma_channel);
630 if (err) {
631 LOG_ERR("Error stopping Tx DMA (%d)", err);
632 goto unlock;
633 }
634
635 evt.type = UART_TX_ABORTED;
636 evt.data.tx.buf = data->async.tx_buf;
637 evt.data.tx.len = data->async.tx_len;
638
639 if (data->async.cb) {
640 data->async.cb(dev, &evt, data->async.user_data);
641 }
642
643 unlock:
644 irq_unlock(key);
645 return err;
646 }
647
uart_esp32_async_tx_timeout(struct k_work * work)648 static void uart_esp32_async_tx_timeout(struct k_work *work)
649 {
650 struct k_work_delayable *dwork = k_work_delayable_from_work(work);
651 struct uart_esp32_async_data *async =
652 CONTAINER_OF(dwork, struct uart_esp32_async_data, tx_timeout_work);
653 struct uart_esp32_data *data = CONTAINER_OF(async, struct uart_esp32_data, async);
654
655 uart_esp32_async_tx_abort(data->uart_dev);
656 }
657
uart_esp32_async_rx_timeout(struct k_work * work)658 static void uart_esp32_async_rx_timeout(struct k_work *work)
659 {
660 struct k_work_delayable *dwork = k_work_delayable_from_work(work);
661 struct uart_esp32_async_data *async =
662 CONTAINER_OF(dwork, struct uart_esp32_async_data, rx_timeout_work);
663 struct uart_esp32_data *data = CONTAINER_OF(async, struct uart_esp32_data, async);
664 const struct uart_esp32_config *config = data->uart_dev->config;
665 struct uart_event evt = {0};
666 int err = 0;
667 unsigned int key = irq_lock();
668
669 evt.type = UART_RX_RDY;
670 evt.data.rx.buf = data->async.rx_buf;
671 evt.data.rx.len = data->async.rx_counter - data->async.rx_offset;
672 evt.data.rx.offset = data->async.rx_offset;
673
674 if (data->async.cb && evt.data.rx.len) {
675 data->async.cb(data->uart_dev, &evt, data->async.user_data);
676 }
677
678 data->async.rx_offset = data->async.rx_counter;
679 k_work_cancel_delayable(&data->async.rx_timeout_work);
680 irq_unlock(key);
681 }
682
uart_esp32_async_callback_set(const struct device * dev,uart_callback_t callback,void * user_data)683 static int uart_esp32_async_callback_set(const struct device *dev, uart_callback_t callback,
684 void *user_data)
685 {
686 struct uart_esp32_data *data = dev->data;
687
688 if (!callback) {
689 return -EINVAL;
690 }
691
692 data->async.cb = callback;
693 data->async.user_data = user_data;
694
695 #if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
696 data->irq_cb = NULL;
697 data->irq_cb_data = NULL;
698 #endif
699
700 return 0;
701 }
702
uart_esp32_async_tx(const struct device * dev,const uint8_t * buf,size_t len,int32_t timeout)703 static int uart_esp32_async_tx(const struct device *dev, const uint8_t *buf, size_t len,
704 int32_t timeout)
705 {
706 const struct uart_esp32_config *config = dev->config;
707 struct uart_esp32_data *data = dev->data;
708 struct dma_config dma_cfg = {0};
709 struct dma_block_config dma_blk = {0};
710 struct dma_status dma_status = {0};
711 int err = 0;
712 unsigned int key = irq_lock();
713
714 if (config->tx_dma_channel == 0xFF) {
715 LOG_ERR("Tx DMA channel is not configured");
716 err = -ENOTSUP;
717 goto unlock;
718 }
719
720 err = dma_get_status(config->dma_dev, config->tx_dma_channel, &dma_status);
721 if (err) {
722 LOG_ERR("Unable to get Tx status (%d)", err);
723 goto unlock;
724 }
725
726 if (dma_status.busy) {
727 LOG_ERR("Tx DMA Channel is busy");
728 err = -EBUSY;
729 goto unlock;
730 }
731
732 data->async.tx_buf = buf;
733 data->async.tx_len = len;
734
735 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
736 dma_cfg.dma_callback = uart_esp32_dma_tx_done;
737 dma_cfg.user_data = (void *)dev;
738 dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_UHCI0;
739 dma_cfg.block_count = 1;
740 dma_cfg.head_block = &dma_blk;
741 dma_blk.block_size = len;
742 dma_blk.source_address = (uint32_t)buf;
743
744 err = dma_config(config->dma_dev, config->tx_dma_channel, &dma_cfg);
745 if (err) {
746 LOG_ERR("Error configuring Tx DMA (%d)", err);
747 goto unlock;
748 }
749
750 uart_esp32_async_timer_start(&data->async.tx_timeout_work, timeout);
751
752 err = dma_start(config->dma_dev, config->tx_dma_channel);
753 if (err) {
754 LOG_ERR("Error starting Tx DMA (%d)", err);
755 goto unlock;
756 }
757
758 unlock:
759 irq_unlock(key);
760 return err;
761 }
762
uart_esp32_async_rx_enable(const struct device * dev,uint8_t * buf,size_t len,int32_t timeout)763 static int uart_esp32_async_rx_enable(const struct device *dev, uint8_t *buf, size_t len,
764 int32_t timeout)
765 {
766 const struct uart_esp32_config *config = dev->config;
767 struct uart_esp32_data *data = dev->data;
768 struct dma_config dma_cfg = {0};
769 struct dma_block_config dma_blk = {0};
770 struct dma_status dma_status = {0};
771 int err = 0;
772 struct uart_event evt = {0};
773
774 if (config->rx_dma_channel == 0xFF) {
775 LOG_ERR("Rx DMA channel is not configured");
776 return -ENOTSUP;
777 }
778
779 err = dma_get_status(config->dma_dev, config->rx_dma_channel, &dma_status);
780 if (err) {
781 LOG_ERR("Unable to get Rx status (%d)", err);
782 return err;
783 }
784
785 if (dma_status.busy) {
786 LOG_ERR("Rx DMA Channel is busy");
787 return -EBUSY;
788 }
789
790 unsigned int key = irq_lock();
791
792 data->async.rx_buf = buf;
793 data->async.rx_len = len;
794 data->async.rx_timeout = timeout;
795
796 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
797 dma_cfg.dma_callback = uart_esp32_dma_rx_done;
798 dma_cfg.user_data = (void *)dev;
799 dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_UHCI0;
800 dma_cfg.block_count = 1;
801 dma_cfg.head_block = &dma_blk;
802 dma_blk.block_size = len;
803 dma_blk.dest_address = (uint32_t)data->async.rx_buf;
804
805 err = dma_config(config->dma_dev, config->rx_dma_channel, &dma_cfg);
806 if (err) {
807 LOG_ERR("Error configuring Rx DMA (%d)", err);
808 goto unlock;
809 }
810
811 /*
812 * Enable interrupt on first receive byte so we can start async timer
813 */
814 uart_hal_set_rxfifo_full_thr(&data->hal, 1);
815 uart_esp32_irq_rx_enable(dev);
816
817 err = dma_start(config->dma_dev, config->rx_dma_channel);
818 if (err) {
819 LOG_ERR("Error starting Rx DMA (%d)", err);
820 goto unlock;
821 }
822
823 data->uhci_dev->pkt_thres.thrs = len;
824
825 /**
826 * Request next buffer
827 */
828 evt.type = UART_RX_BUF_REQUEST;
829 if (data->async.cb) {
830 data->async.cb(dev, &evt, data->async.user_data);
831 }
832
833 unlock:
834 irq_unlock(key);
835 return err;
836 }
837
uart_esp32_async_rx_buf_rsp(const struct device * dev,uint8_t * buf,size_t len)838 static int uart_esp32_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
839 {
840 const struct uart_esp32_config *config = dev->config;
841 struct uart_esp32_data *data = dev->data;
842
843 data->async.rx_next_buf = buf;
844 data->async.rx_next_len = len;
845
846 return 0;
847 }
848
uart_esp32_async_rx_disable(const struct device * dev)849 static int uart_esp32_async_rx_disable(const struct device *dev)
850 {
851 const struct uart_esp32_config *config = dev->config;
852 struct uart_esp32_data *data = dev->data;
853 unsigned int key = irq_lock();
854 int err = 0;
855 struct uart_event evt = {0};
856
857 k_work_cancel_delayable(&data->async.rx_timeout_work);
858
859 if (!data->async.rx_len) {
860 err = -EINVAL;
861 goto unlock;
862 }
863
864 err = dma_stop(config->dma_dev, config->rx_dma_channel);
865 if (err) {
866 LOG_ERR("Error stopping Rx DMA (%d)", err);
867 goto unlock;
868 }
869
870 /*If any bytes have been received notify RX_RDY*/
871 evt.type = UART_RX_RDY;
872 evt.data.rx.buf = data->async.rx_buf;
873 evt.data.rx.len = data->async.rx_counter - data->async.rx_offset;
874 evt.data.rx.offset = data->async.rx_offset;
875
876 if (data->async.cb && evt.data.rx.len) {
877 data->async.cb(data->uart_dev, &evt, data->async.user_data);
878 }
879
880 data->async.rx_offset = 0;
881 data->async.rx_counter = 0;
882
883 /* Release current buffer*/
884 evt.type = UART_RX_BUF_RELEASED;
885 evt.data.rx_buf.buf = data->async.rx_buf;
886
887 if (data->async.cb) {
888 data->async.cb(dev, &evt, data->async.user_data);
889 }
890
891 data->async.rx_len = 0;
892 data->async.rx_buf = NULL;
893
894 /*Release next buffer*/
895 if (data->async.rx_next_len) {
896 evt.type = UART_RX_BUF_RELEASED;
897 evt.data.rx_buf.buf = data->async.rx_next_buf;
898 if (data->async.cb) {
899 data->async.cb(dev, &evt, data->async.user_data);
900 }
901
902 data->async.rx_next_len = 0;
903 data->async.rx_next_buf = NULL;
904 }
905
906 /*Notify UART_RX_DISABLED*/
907 evt.type = UART_RX_DISABLED;
908 if (data->async.cb) {
909 data->async.cb(dev, &evt, data->async.user_data);
910 }
911
912 unlock:
913 irq_unlock(key);
914 return err;
915 }
916
917 #endif /* CONFIG_UART_ASYNC_API */
918
uart_esp32_init(const struct device * dev)919 static int uart_esp32_init(const struct device *dev)
920 {
921 const struct uart_esp32_config *config = dev->config;
922 struct uart_esp32_data *data = dev->data;
923 int ret = uart_esp32_configure(dev, &data->uart_config);
924
925 if (ret < 0) {
926 LOG_ERR("Error configuring UART (%d)", ret);
927 return ret;
928 }
929
930 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
931 ret = esp_intr_alloc(config->irq_source,
932 config->irq_priority,
933 (ISR_HANDLER)uart_esp32_isr,
934 (void *)dev,
935 NULL);
936 if (ret < 0) {
937 LOG_ERR("Error allocating UART interrupt (%d)", ret);
938 return ret;
939 }
940 #endif
941 #if CONFIG_UART_ASYNC_API
942 if (config->dma_dev) {
943 if (!device_is_ready(config->dma_dev)) {
944 LOG_ERR("DMA device is not ready");
945 return -ENODEV;
946 }
947
948 clock_control_on(config->clock_dev, (clock_control_subsys_t)ESP32_UHCI0_MODULE);
949 uhci_ll_init(data->uhci_dev);
950 uhci_ll_set_eof_mode(data->uhci_dev, UHCI_RX_IDLE_EOF | UHCI_RX_LEN_EOF);
951 uhci_ll_attach_uart_port(data->uhci_dev, uart_hal_get_port_num(&data->hal));
952 data->uart_dev = dev;
953
954 k_work_init_delayable(&data->async.tx_timeout_work, uart_esp32_async_tx_timeout);
955 k_work_init_delayable(&data->async.rx_timeout_work, uart_esp32_async_rx_timeout);
956 }
957 #endif
958 return 0;
959 }
960
961 static const DRAM_ATTR struct uart_driver_api uart_esp32_api = {
962 .poll_in = uart_esp32_poll_in,
963 .poll_out = uart_esp32_poll_out,
964 .err_check = uart_esp32_err_check,
965 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
966 .configure = uart_esp32_configure,
967 .config_get = uart_esp32_config_get,
968 #endif
969 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
970 .fifo_fill = uart_esp32_fifo_fill,
971 .fifo_read = uart_esp32_fifo_read,
972 .irq_tx_enable = uart_esp32_irq_tx_enable,
973 .irq_tx_disable = uart_esp32_irq_tx_disable,
974 .irq_tx_ready = uart_esp32_irq_tx_ready,
975 .irq_rx_enable = uart_esp32_irq_rx_enable,
976 .irq_rx_disable = uart_esp32_irq_rx_disable,
977 .irq_tx_complete = uart_esp32_irq_tx_complete,
978 .irq_rx_ready = uart_esp32_irq_rx_ready,
979 .irq_err_enable = uart_esp32_irq_err_enable,
980 .irq_err_disable = uart_esp32_irq_err_disable,
981 .irq_is_pending = uart_esp32_irq_is_pending,
982 .irq_update = uart_esp32_irq_update,
983 .irq_callback_set = uart_esp32_irq_callback_set,
984 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
985 #if CONFIG_UART_ASYNC_API
986 .callback_set = uart_esp32_async_callback_set,
987 .tx = uart_esp32_async_tx,
988 .tx_abort = uart_esp32_async_tx_abort,
989 .rx_enable = uart_esp32_async_rx_enable,
990 .rx_buf_rsp = uart_esp32_async_rx_buf_rsp,
991 .rx_disable = uart_esp32_async_rx_disable,
992 #endif /*CONFIG_UART_ASYNC_API*/
993 };
994
995 #if CONFIG_UART_ASYNC_API
996 #define ESP_UART_DMA_INIT(n) \
997 .dma_dev = ESP32_DT_INST_DMA_CTLR(n, tx), \
998 .tx_dma_channel = ESP32_DT_INST_DMA_CELL(n, tx, channel), \
999 .rx_dma_channel = ESP32_DT_INST_DMA_CELL(n, rx, channel)
1000
1001 #define ESP_UART_UHCI_INIT(n) \
1002 .uhci_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (&UHCI0), (NULL))
1003
1004 #define UART_IRQ_PRIORITY ESP_INTR_FLAG_LEVEL2
1005
1006 #else
1007 #define ESP_UART_DMA_INIT(n)
1008 #define ESP_UART_UHCI_INIT(n)
1009 #define UART_IRQ_PRIORITY (0)
1010 #endif
1011
1012 #define ESP32_UART_INIT(idx) \
1013 \
1014 PINCTRL_DT_INST_DEFINE(idx); \
1015 \
1016 static const DRAM_ATTR struct uart_esp32_config uart_esp32_cfg_port_##idx = { \
1017 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
1018 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
1019 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
1020 .irq_source = DT_INST_IRQN(idx), \
1021 .irq_priority = UART_IRQ_PRIORITY, \
1022 .tx_invert = DT_INST_PROP_OR(idx, tx_invert, false), \
1023 .rx_invert = DT_INST_PROP_OR(idx, rx_invert, false), \
1024 ESP_UART_DMA_INIT(idx)}; \
1025 \
1026 static struct uart_esp32_data uart_esp32_data_##idx = { \
1027 .uart_config = {.baudrate = DT_INST_PROP(idx, current_speed), \
1028 .parity = DT_INST_ENUM_IDX_OR(idx, parity, UART_CFG_PARITY_NONE), \
1029 .stop_bits = DT_INST_ENUM_IDX_OR(idx, stop_bits, \
1030 UART_CFG_STOP_BITS_1), \
1031 .data_bits = DT_INST_ENUM_IDX_OR(idx, data_bits, \
1032 UART_CFG_DATA_BITS_8), \
1033 .flow_ctrl = MAX(COND_CODE_1(DT_INST_PROP(idx, hw_rs485_hd_mode), \
1034 (UART_CFG_FLOW_CTRL_RS485), \
1035 (UART_CFG_FLOW_CTRL_NONE)), \
1036 COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
1037 (UART_CFG_FLOW_CTRL_RTS_CTS), \
1038 (UART_CFG_FLOW_CTRL_NONE)))}, \
1039 .hal = \
1040 { \
1041 .dev = (uart_dev_t *)DT_INST_REG_ADDR(idx), \
1042 }, \
1043 ESP_UART_UHCI_INIT(idx)}; \
1044 \
1045 DEVICE_DT_INST_DEFINE(idx, uart_esp32_init, NULL, &uart_esp32_data_##idx, \
1046 &uart_esp32_cfg_port_##idx, PRE_KERNEL_1, \
1047 CONFIG_SERIAL_INIT_PRIORITY, &uart_esp32_api);
1048
1049 DT_INST_FOREACH_STATUS_OKAY(ESP32_UART_INIT);
1050
