1 /* 2 * Copyright (c) 2017, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/drivers/sensor.h> 8 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 9 #include <zephyr/drivers/i2c.h> 10 #endif 11 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 12 #include <zephyr/drivers/spi.h> 13 #endif 14 #include <zephyr/drivers/gpio.h> 15 #include <zephyr/kernel.h> 16 17 #define FXAS21002_BUS_I2C (1<<0) 18 #define FXAS21002_BUS_SPI (1<<1) 19 #define FXAS21002_REG_STATUS 0x00 20 #define FXAS21002_REG_OUTXMSB 0x01 21 #define FXAS21002_REG_INT_SOURCE 0x0b 22 #define FXAS21002_REG_WHOAMI 0x0c 23 #define FXAS21002_REG_CTRLREG0 0x0d 24 #define FXAS21002_REG_CTRLREG1 0x13 25 #define FXAS21002_REG_CTRLREG2 0x14 26 #define FXAS21002_REG_CTRLREG3 0x15 27 28 #define FXAS21002_INT_SOURCE_DRDY_MASK (1 << 0) 29 30 #define FXAS21002_CTRLREG0_FS_MASK (3 << 0) 31 32 #define FXAS21002_CTRLREG1_DR_SHIFT 2 33 34 #define FXAS21002_CTRLREG1_POWER_MASK (3 << 0) 35 #define FXAS21002_CTRLREG1_DR_MASK (7 << FXAS21002_CTRLREG1_DR_SHIFT) 36 #define FXAS21002_CTRLREG1_RST_MASK (1 << 6) 37 38 #define FXAS21002_CTRLREG2_CFG_EN_MASK (1 << 2) 39 #define FXAS21002_CTRLREG2_CFG_DRDY_MASK (1 << 3) 40 41 #define FXAS21002_MAX_NUM_CHANNELS 3 42 43 #define FXAS21002_BYTES_PER_CHANNEL 2 44 45 #define FXAS21002_MAX_NUM_BYTES (FXAS21002_BYTES_PER_CHANNEL * \ 46 FXAS21002_MAX_NUM_CHANNELS) 47 48 enum fxas21002_power { 49 FXAS21002_POWER_STANDBY = 0, 50 FXAS21002_POWER_READY = 1, 51 FXAS21002_POWER_ACTIVE = 3, 52 }; 53 54 enum fxas21002_range { 55 FXAS21002_RANGE_2000DPS = 0, 56 FXAS21002_RANGE_1000DPS, 57 FXAS21002_RANGE_500DPS, 58 FXAS21002_RANGE_250DPS, 59 }; 60 61 enum fxas21002_channel { 62 FXAS21002_CHANNEL_GYRO_X = 0, 63 FXAS21002_CHANNEL_GYRO_Y, 64 FXAS21002_CHANNEL_GYRO_Z, 65 }; 66 67 struct fxas21002_io_ops { 68 int (*read)(const struct device *dev, 69 uint8_t reg, 70 void *data, 71 size_t length); 72 int (*byte_read)(const struct device *dev, 73 uint8_t reg, 74 uint8_t *byte); 75 int (*byte_write)(const struct device *dev, 76 uint8_t reg, 77 uint8_t byte); 78 int (*reg_field_update)(const struct device *dev, 79 uint8_t reg, 80 uint8_t mask, 81 uint8_t val); 82 }; 83 84 union fxas21002_bus_cfg { 85 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 86 struct spi_dt_spec spi; 87 #endif 88 89 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 90 struct i2c_dt_spec i2c; 91 #endif 92 }; 93 94 struct fxas21002_config { 95 const union fxas21002_bus_cfg bus_cfg; 96 const struct fxas21002_io_ops *ops; 97 #ifdef CONFIG_FXAS21002_TRIGGER 98 struct gpio_dt_spec int_gpio; 99 #endif 100 struct gpio_dt_spec reset_gpio; 101 uint8_t whoami; 102 enum fxas21002_range range; 103 uint8_t dr; 104 uint8_t inst_on_bus; 105 }; 106 107 struct fxas21002_data { 108 struct k_sem sem; 109 #ifdef CONFIG_FXAS21002_TRIGGER 110 const struct device *dev; 111 struct gpio_callback gpio_cb; 112 sensor_trigger_handler_t drdy_handler; 113 const struct sensor_trigger *drdy_trig; 114 #endif 115 #ifdef CONFIG_FXAS21002_TRIGGER_OWN_THREAD 116 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_FXAS21002_THREAD_STACK_SIZE); 117 struct k_thread thread; 118 struct k_sem trig_sem; 119 #endif 120 #ifdef CONFIG_FXAS21002_TRIGGER_GLOBAL_THREAD 121 struct k_work work; 122 #endif 123 int16_t raw[FXAS21002_MAX_NUM_CHANNELS]; 124 }; 125 126 int fxas21002_get_power(const struct device *dev, enum fxas21002_power *power); 127 int fxas21002_set_power(const struct device *dev, enum fxas21002_power power); 128 129 uint32_t fxas21002_get_transition_time(enum fxas21002_power start, 130 enum fxas21002_power end, 131 uint8_t dr); 132 133 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 134 int fxas21002_byte_write_spi(const struct device *dev, 135 uint8_t reg, 136 uint8_t byte); 137 138 int fxas21002_byte_read_spi(const struct device *dev, 139 uint8_t reg, 140 uint8_t *byte); 141 142 int fxas21002_reg_field_update_spi(const struct device *dev, 143 uint8_t reg, 144 uint8_t mask, 145 uint8_t val); 146 147 int fxas21002_read_spi(const struct device *dev, 148 uint8_t reg, 149 void *data, 150 size_t length); 151 #endif 152 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 153 int fxas21002_byte_write_i2c(const struct device *dev, 154 uint8_t reg, 155 uint8_t byte); 156 157 int fxas21002_byte_read_i2c(const struct device *dev, 158 uint8_t reg, 159 uint8_t *byte); 160 161 int fxas21002_reg_field_update_i2c(const struct device *dev, 162 uint8_t reg, 163 uint8_t mask, 164 uint8_t val); 165 166 int fxas21002_read_i2c(const struct device *dev, 167 uint8_t reg, 168 void *data, 169 size_t length); 170 #endif 171 #if CONFIG_FXAS21002_TRIGGER 172 int fxas21002_trigger_init(const struct device *dev); 173 int fxas21002_trigger_set(const struct device *dev, 174 const struct sensor_trigger *trig, 175 sensor_trigger_handler_t handler); 176 #endif 177
