1 /* 2 * Copyright (C) 2023 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #include <zephyr/cache.h> 7 #include <zephyr/drivers/sdhc.h> 8 9 /* HRS09 */ 10 #define CDNS_HRS09_PHY_SW_RESET BIT(0) 11 #define CDNS_HRS09_PHY_INIT_COMP BIT(1) 12 #define CDNS_HRS09_EXT_WR_MODE BIT(3) 13 #define CDNS_HRS09_RDCMD_EN_BIT BIT(15) 14 #define CDNS_HRS09_RDDATA_EN_BIT BIT(16) 15 #define CDNS_HRS09_EXT_RD_MODE(x) ((x) << 2) 16 #define CDNS_HRS09_EXTENDED_WR(x) ((x) << 3) 17 #define CDNS_HRS09_RDCMD_EN(x) ((x) << 15) 18 #define CDNS_HRS09_RDDATA_EN(x) ((x) << 16) 19 20 /* HRS00 */ 21 #define CDNS_HRS00_SWR BIT(0) 22 23 /* CMD_DATA_OUTPUT */ 24 #define SDHC_CDNS_HRS16 0x40 25 26 /* SRS09 - Present State Register */ 27 #define CDNS_SRS09_STAT_DAT_BUSY BIT(2) 28 #define CDNS_SRS09_CI BIT(16) 29 30 /* SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up) */ 31 #define LEDC BIT(0) 32 #define DT_WIDTH BIT(1) 33 #define HS_EN BIT(2) 34 35 #define CDNS_SRS10_DTW 1 36 #define CDNS_SRS10_EDTW 5 37 #define CDNS_SRS10_BP BIT(8) 38 39 #define CDNS_SRS10_BVS 9 40 #define BUS_VOLTAGE_1_8_V (5 << CDNS_SRS10_BVS) 41 #define BUS_VOLTAGE_3_0_V (6 << CDNS_SRS10_BVS) 42 #define BUS_VOLTAGE_3_3_V (7 << CDNS_SRS10_BVS) 43 44 45 /* data bus width */ 46 #define WIDTH_BIT1 CDNS_SRS10_DTW 47 #define WIDTH_BIT4 CDNS_SRS10_DTW 48 #define WIDTH_BIT8 CDNS_SRS10_EDTW 49 50 /* SRS11 */ 51 #define CDNS_SRS11_ICE BIT(0) 52 #define CDNS_SRS11_ICS BIT(1) 53 #define CDNS_SRS11_SDCE BIT(2) 54 #define CDNS_SRS11_USDCLKFS 6 55 #define CDNS_SRS11_SDCLKFS 8 56 #define CDNS_SRS11_DTCV 16 57 #define CDNS_SRS11_SRFA BIT(24) 58 #define CDNS_SRS11_SRCMD BIT(25) 59 #define CDNS_SRS11_SRDAT BIT(26) 60 61 /* 62 * This value determines the interval by which DAT line timeouts are detected 63 * The interval can be computed as below: 64 * • 1111b - Reserved 65 * • 1110b - t_sdmclk*2(27+2) 66 * • 1101b - t_sdmclk*2(26+2) 67 */ 68 #define DTC_VAL 0xE 69 #define READ_CLK (0xa << CDNS_SRS11_DTCV) 70 #define WRITE_CLK (0xe << CDNS_SRS11_DTCV) 71 72 73 /* SRS12 */ 74 #define CDNS_SRS12_CC BIT(0) 75 #define CDNS_SRS12_TC BIT(1) 76 #define CDNS_SRS12_EINT BIT(15) 77 78 /* SDMA Buffer Boundary */ 79 #define BUFFER_BOUNDARY_4K 0U 80 #define BUFFER_BOUNDARY_8K 1U 81 #define BUFFER_BOUNDARY_16K 2U 82 #define BUFFER_BOUNDARY_32K 3U 83 #define BUFFER_BOUNDARY_64K 4U 84 #define BUFFER_BOUNDARY_128K 5U 85 #define BUFFER_BOUNDARY_256K 6U 86 #define BUFFER_BOUNDARY_512K 7U 87 88 /* SRS01 */ 89 #define CDNS_SRS01_BLK_SIZE 0U 90 #define CDNS_SRS01_SDMA_BUF 12 91 #define CDNS_SRS01_BLK_COUNT_CT 16 92 93 /* SRS15 Registers */ 94 #define CDNS_SRS15_UMS 16 95 #define CDNS_SRS15_SDR12 (0 << CDNS_SRS15_UMS) 96 #define CDNS_SRS15_SDR25 (1 << CDNS_SRS15_UMS) 97 #define CDNS_SRS15_SDR50 (2 << CDNS_SRS15_UMS) 98 #define CDNS_SRS15_SDR104 (3 << CDNS_SRS15_UMS) 99 #define CDNS_SRS15_DDR50 (4 << CDNS_SRS15_UMS) 100 /* V18SE is 0 for DS and HS, 1 for UHS-I */ 101 #define CDNS_SRS15_V18SE BIT(19) 102 #define CDNS_SRS15_CMD23_EN BIT(27) 103 /* HC4E is 0 means version 3.0 and 1 means v 4.0 */ 104 #define CDNS_SRS15_HV4E BIT(28) 105 #define CDNS_SRS15_BIT_AD_32 0U 106 #define CDNS_SRS15_BIT_AD_64 BIT(29) 107 #define CDNS_SRS15_PVE BIT(31) 108 109 /* Combo PHY */ 110 #define PHY_DQ_TIMING_REG 0x0 111 #define PHY_DQS_TIMING_REG 0x04 112 #define PHY_GATE_LPBK_CTRL_REG 0x08 113 #define PHY_DLL_MASTER_CTRL_REG 0x0C 114 #define PHY_DLL_SLAVE_CTRL_REG 0x10 115 #define PHY_CTRL_REG 0x80 116 117 #define PERIPHERAL_SDMMC_MASK 0x60 118 #define PERIPHERAL_SDMMC_OFFSET 6 119 #define DFI_INTF_MASK 0x1 120 121 /* PHY_DQS_TIMING_REG */ 122 #define CP_USE_EXT_LPBK_DQS(x) (x << 22) 123 #define CP_USE_LPBK_DQS(x) (x << 21) 124 #define CP_USE_PHONY_DQS(x) (x << 20) 125 #define CP_USE_PHONY_DQS_CMD(x) (x << 19) 126 127 /* PHY_GATE_LPBK_CTRL_REG */ 128 #define CP_SYNC_METHOD(x) ((x) << 31) 129 #define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) 130 #define CP_RD_DEL_SEL(x) ((x) << 19) 131 #define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) 132 #define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) 133 134 /* PHY_DLL_MASTER_CTRL_REG */ 135 #define CP_DLL_BYPASS_MODE(x) ((x) << 23) 136 #define CP_DLL_START_POINT(x) ((x) << 0) 137 138 /* PHY_DLL_SLAVE_CTRL_REG */ 139 #define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) 140 #define CP_CLK_WRDQS_DELAY(x) ((x) << 16) 141 #define CP_CLK_WR_DELAY(x) ((x) << 8) 142 #define CP_READ_DQS_DELAY(x) (x) 143 144 /* PHY_DQ_TIMING_REG */ 145 #define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) 146 #define CP_IO_MASK_END(x) ((x) << 27) 147 #define CP_IO_MASK_START(x) ((x) << 24) 148 #define CP_DATA_SELECT_OE_END(x) (x) 149 150 /* SW RESET REG */ 151 #define SDHC_CDNS_HRS00 (0x00) 152 #define CDNS_HRS00_SWR BIT(0) 153 154 /* PHY access port */ 155 #define SDHC_CDNS_HRS04 0x10 156 #define CDNS_HRS04_ADDR GENMASK(5, 0) 157 158 /* PHY data access port */ 159 #define SDHC_CDNS_HRS05 0x14 160 161 /* eMMC control registers */ 162 #define SDHC_CDNS_HRS06 0x18 163 164 /* PHY_CTRL_REG */ 165 #define CP_PHONY_DQS_TIMING_MASK 0x3F 166 #define CP_PHONY_DQS_TIMING_SHIFT 4 167 168 /* SRS */ 169 #define SDHC_CDNS_SRS00 0x200 170 #define SDHC_CDNS_SRS01 0x204 171 #define SDHC_CDNS_SRS02 0x208 172 #define SDHC_CDNS_SRS03 0x20c 173 #define SDHC_CDNS_SRS04 0x210 174 #define SDHC_CDNS_SRS05 0x214 175 #define SDHC_CDNS_SRS06 0x218 176 #define SDHC_CDNS_SRS07 0x21C 177 #define SDHC_CDNS_SRS08 0x220 178 #define SDHC_CDNS_SRS09 0x224 179 #define SDHC_CDNS_SRS10 0x228 180 #define SDHC_CDNS_SRS11 0x22C 181 #define SDHC_CDNS_SRS12 0x230 182 #define SDHC_CDNS_SRS13 0x234 183 #define SDHC_CDNS_SRS14 0x238 184 #define SDHC_CDNS_SRS15 0x23c 185 #define SDHC_CDNS_SRS21 0x254 186 #define SDHC_CDNS_SRS22 0x258 187 #define SDHC_CDNS_SRS23 0x25c 188 189 /* SRS00 */ 190 #define CDNS_SRS00_SAAR 1 191 192 /* SRS03 */ 193 #define CDNS_SRS03_CMD_START BIT(31) 194 #define CDNS_SRS03_CMD_USE_HOLD_REG BIT(29) 195 #define CDNS_SRS03_COM_IDX 24 196 197 /* Command type */ 198 #define CDNS_SRS03_CMD_TYPE 22 199 #define CMD_STOP_ABORT_CMD (3 << CDNS_SRS03_CMD_TYPE) 200 #define CMD_RESUME_CMD (2 << CDNS_SRS03_CMD_TYPE) 201 #define CMD_SUSPEND_CMD (1 << CDNS_SRS03_CMD_TYPE) 202 203 #define CDNS_SRS03_DATA_PRSNT BIT(21) 204 #define CDNS_SRS03_CMD_IDX_CHK_EN BIT(20) 205 #define CDNS_SRS03_RESP_CRCCE BIT(19) 206 #define CDNS_SRS03_RESP_ERR BIT(7) 207 #define CDNS_SRS03_MULTI_BLK_READ BIT(5) 208 #define CDNS_SRS03_CMD_READ BIT(4) 209 210 /* Response type select */ 211 #define CDNS_SRS03_RES_TYPE_SEL 16 212 #define RES_TYPE_SEL_NO (0 << CDNS_SRS03_RES_TYPE_SEL) 213 #define RES_TYPE_SEL_136 (1 << CDNS_SRS03_RES_TYPE_SEL) 214 #define RES_TYPE_SEL_48 (2 << CDNS_SRS03_RES_TYPE_SEL) 215 #define RES_TYPE_SEL_48_B (3 << CDNS_SRS03_RES_TYPE_SEL) 216 217 /* Auto CMD Enable */ 218 #define CDNS_SRS03_ACE 2 219 #define NO_AUTO_COMMAND (0 << CDNS_SRS03_ACE) 220 #define AUTO_CMD12 (1 << CDNS_SRS03_ACE) 221 #define AUTO_CMD23 (2 << CDNS_SRS03_ACE) 222 #define AUTO_CMD_AUTO (3 << CDNS_SRS03_ACE) 223 224 #define CDNS_SRS03_DMA_EN BIT(0) 225 #define CDNS_SRS03_BLK_CNT_EN BIT(1) 226 227 /* HRS07 - IO Delay Information Register */ 228 #define SDHC_CDNS_HRS07 0x1c 229 #define CDNS_HRS07_IDELAY_VAL(x) (x) 230 #define CDNS_HRS07_RW_COMPENSATE(x) ((x) << 16) 231 232 /* HRS09 - PHY Control and Status Register */ 233 #define SDHC_CDNS_HRS09 0x24 234 235 /* HRS10 - Host Controller SDCLK start point adjustment */ 236 #define SDHC_CDNS_HRS10 0x28 237 238 /* HCSDCLKADJ DATA; DDR Mode */ 239 #define SDHC_HRS10_HCSDCLKADJ(x) ((x) << 16) 240 241 /* HRS16 */ 242 #define CDNS_HRS16_WRCMD0_DLY(x) (x) 243 #define CDNS_HRS16_WRCMD1_DLY(x) ((x) << 4) 244 #define CDNS_HRS16_WRDATA0_DLY(x) ((x) << 8) 245 #define CDNS_HRS16_WRDATA1_DLY(x) ((x) << 12) 246 #define CDNS_HRS16_WRCMD0_SDCLK_DLY(x) ((x) << 16) 247 #define CDNS_HRS16_WRCMD1_SDCLK_DLY(x) ((x) << 20) 248 #define CDNS_HRS16_WRDATA0_SDCLK_DLY(x) ((x) << 24) 249 #define CDNS_HRS16_WRDATA1_SDCLK_DLY(x) ((x) << 28) 250 251 /* Shared Macros */ 252 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ 253 (SDMMC_CDN_##_reg)) 254 255 /* MMC Peripheral Definition */ 256 #define MMC_BLOCK_SIZE 512U 257 #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - 1) 258 #define MMC_BOOT_CLK_RATE (400 * 1000) 259 260 #define OCR_POWERUP BIT(31) 261 #define OCR_HCS BIT(30) 262 263 #define OCR_3_5_3_6 BIT(23) 264 #define OCR_3_4_3_5 BIT(22) 265 #define OCR_3_3_3_4 BIT(21) 266 #define OCR_3_2_3_3 BIT(20) 267 #define OCR_3_1_3_2 BIT(19) 268 #define OCR_3_0_3_1 BIT(18) 269 #define OCR_2_9_3_0 BIT(17) 270 #define OCR_2_8_2_9 BIT(16) 271 #define OCR_2_7_2_8 BIT(15) 272 #define OCR_VDD_MIN_2V7 GENMASK(23, 15) 273 #define OCR_VDD_MIN_2V0 GENMASK(14, 8) 274 #define OCR_VDD_MIN_1V7 BIT(7) 275 276 #define MMC_RSP_48 BIT(0) 277 #define MMC_RSP_136 BIT(1) /* 136 bit response */ 278 #define MMC_RSP_CRC BIT(2) /* expect valid crc */ 279 #define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */ 280 #define MMC_RSP_BUSY BIT(4) /* device may be busy */ 281 282 /* JEDEC 4.51 chapter 6.12 */ 283 #define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC) 284 #define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY) 285 #define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC) 286 #define MMC_RESPONSE_R3 (MMC_RSP_48) 287 #define MMC_RESPONSE_R4 (MMC_RSP_48) 288 #define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 289 #define MMC_RESPONSE_R6 (MMC_RSP_CRC | MMC_RSP_CMD_IDX) 290 #define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC) 291 #define MMC_RESPONSE_NONE 0 292 293 /* Value randomly chosen for eMMC RCA, it should be > 1 */ 294 #define MMC_FIX_RCA 6 295 #define RCA_SHIFT_OFFSET 16 296 297 #define CMD_EXTCSD_PARTITION_CONFIG 179 298 #define CMD_EXTCSD_BUS_WIDTH 183 299 #define CMD_EXTCSD_HS_TIMING 185 300 #define CMD_EXTCSD_SEC_CNT 212 301 302 #define PART_CFG_BOOT_PARTITION1_ENABLE BIT(3) 303 #define PART_CFG_PARTITION1_ACCESS 1 304 305 /* Values in EXT CSD register */ 306 #define MMC_BUS_WIDTH_1 0 307 #define MMC_BUS_WIDTH_4 1 308 #define MMC_BUS_WIDTH_8 2 309 #define MMC_BUS_WIDTH_DDR_4 5 310 #define MMC_BUS_WIDTH_DDR_8 6 311 #define MMC_BOOT_MODE_BACKWARD 0 312 #define MMC_BOOT_MODE_HS_TIMING BIT(3) 313 #define MMC_BOOT_MODE_DDR (2 << 3) 314 315 #define EXTCSD_SET_CMD 0 316 #define EXTCSD_SET_BITS BIT(24) 317 #define EXTCSD_CLR_BITS (2 << 24) 318 #define EXTCSD_WRITE_BYTES (3 << 24) 319 #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 320 #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 321 #define EXTCSD_CMD_SET_NORMAL 1 322 323 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 324 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 325 #define CSD_TRAN_SPEED_MULT_SHIFT 3 326 327 #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 328 #define STATUS_READY_FOR_DATA BIT(8) 329 #define STATUS_SWITCH_ERROR BIT(7) 330 #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 331 #define MMC_STATE_IDLE 0 332 #define MMC_STATE_READY 1 333 #define MMC_STATE_IDENT 2 334 #define MMC_STATE_STBY 3 335 #define MMC_STATE_TRAN 4 336 #define MMC_STATE_DATA 5 337 #define MMC_STATE_RCV 6 338 #define MMC_STATE_PRG 7 339 #define MMC_STATE_DIS 8 340 #define MMC_STATE_BTST 9 341 #define MMC_STATE_SLP 10 342 343 #define MMC_FLAG_CMD23 1 344 345 #define CMD8_CHECK_PATTERN 0xAA 346 #define VHS_2_7_3_6_V BIT(8) 347 348 #define SD_SCR_BUS_WIDTH_1 BIT(8) 349 #define SD_SCR_BUS_WIDTH_4 BIT(10) 350 351 /* ADMA table component */ 352 #define ADMA_DESC_ATTR_VALID BIT(0) 353 #define ADMA_DESC_ATTR_END BIT(1) 354 #define ADMA_DESC_ATTR_INT BIT(2) 355 #define ADMA_DESC_ATTR_ACT1 BIT(4) 356 #define ADMA_DESC_ATTR_ACT2 BIT(5) 357 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 358 359 /* Conf depends on SRS15.HV4E */ 360 #define SDMA 0 361 #define ADMA2_32 (2 << 3) 362 #define ADMA2_64 (3 << 3) 363 /* here 0 defines the 64 Kb size */ 364 #define MAX_64KB_PAGE 0 365 366 struct sdmmc_cmd { 367 unsigned int cmd_idx; 368 unsigned int cmd_arg; 369 unsigned int resp_type; 370 unsigned int resp_data[4]; 371 }; 372 373 struct sdhc_cdns_ops { 374 /* init function for card */ 375 int (*init)(void); 376 /* busy check function for card */ 377 int (*busy)(void); 378 /* card_present function check for card */ 379 int (*card_present)(void); 380 /* reset the card */ 381 int (*reset)(void); 382 /* send command and respective argument */ 383 int (*send_cmd)(struct sdmmc_cmd *cmd, struct sdhc_data *data); 384 /* io set up for card */ 385 int (*set_ios)(unsigned int clk, unsigned int width); 386 /* prepare dma descriptors */ 387 int (*prepare)(uint32_t lba, uintptr_t buf, struct sdhc_data *data); 388 /* cache invd api */ 389 int (*cache_invd)(int lba, uintptr_t buf, size_t size); 390 }; 391 392 /* Combo Phy reg */ 393 struct sdhc_cdns_combo_phy { 394 uint32_t cp_clk_wr_delay; 395 uint32_t cp_clk_wrdqs_delay; 396 uint32_t cp_data_select_oe_end; 397 uint32_t cp_dll_bypass_mode; 398 uint32_t cp_dll_locked_mode; 399 uint32_t cp_dll_start_point; 400 uint32_t cp_gate_cfg_always_on; 401 uint32_t cp_io_mask_always_on; 402 uint32_t cp_io_mask_end; 403 uint32_t cp_io_mask_start; 404 uint32_t cp_rd_del_sel; 405 uint32_t cp_read_dqs_cmd_delay; 406 uint32_t cp_read_dqs_delay; 407 uint32_t cp_sw_half_cycle_shift; 408 uint32_t cp_sync_method; 409 uint32_t cp_underrun_suppress; 410 uint32_t cp_use_ext_lpbk_dqs; 411 uint32_t cp_use_lpbk_dqs; 412 uint32_t cp_use_phony_dqs; 413 uint32_t cp_use_phony_dqs_cmd; 414 }; 415 416 /* sdmmc reg */ 417 struct sdhc_cdns_sdmmc { 418 uint32_t sdhc_extended_rd_mode; 419 uint32_t sdhc_extended_wr_mode; 420 uint32_t sdhc_hcsdclkadj; 421 uint32_t sdhc_idelay_val; 422 uint32_t sdhc_rdcmd_en; 423 uint32_t sdhc_rddata_en; 424 uint32_t sdhc_rw_compensate; 425 uint32_t sdhc_sdcfsh; 426 uint32_t sdhc_sdcfsl; 427 uint32_t sdhc_wrcmd0_dly; 428 uint32_t sdhc_wrcmd0_sdclk_dly; 429 uint32_t sdhc_wrcmd1_dly; 430 uint32_t sdhc_wrcmd1_sdclk_dly; 431 uint32_t sdhc_wrdata0_dly; 432 uint32_t sdhc_wrdata0_sdclk_dly; 433 uint32_t sdhc_wrdata1_dly; 434 uint32_t sdhc_wrdata1_sdclk_dly; 435 }; 436 437 enum sdmmc_device_mode { 438 /* Identification */ 439 SD_DS_ID, 440 /* Default speed */ 441 SD_DS, 442 /* High speed */ 443 SD_HS, 444 /* Ultra high speed SDR12 */ 445 SD_UHS_SDR12, 446 /* Ultra high speed SDR25 */ 447 SD_UHS_SDR25, 448 /* Ultra high speed SDR`50 */ 449 SD_UHS_SDR50, 450 /* Ultra high speed SDR104 */ 451 SD_UHS_SDR104, 452 /* Ultra high speed DDR50 */ 453 SD_UHS_DDR50, 454 /* SDR backward compatible */ 455 EMMC_SDR_BC, 456 /* SDR */ 457 EMMC_SDR, 458 /* DDR */ 459 EMMC_DDR, 460 /* High speed 200Mhz in SDR */ 461 EMMC_HS200, 462 /* High speed 200Mhz in DDR */ 463 EMMC_HS400, 464 /* High speed 200Mhz in SDR with enhanced strobe */ 465 EMMC_HS400ES, 466 }; 467 468 struct sdhc_cdns_params { 469 uintptr_t reg_base; 470 uintptr_t reg_phy; 471 uintptr_t desc_base; 472 size_t desc_size; 473 int clk_rate; 474 int bus_width; 475 unsigned int flags; 476 enum sdmmc_device_mode cdn_sdmmc_dev_type; 477 uint32_t combophy; 478 }; 479 480 struct sdmmc_device_info { 481 /* Size of device in bytes */ 482 unsigned long long device_size; 483 /* Block size in bytes */ 484 unsigned int block_size; 485 /* Max bus freq in Hz */ 486 unsigned int max_bus_freq; 487 /* OCR voltage */ 488 unsigned int ocr_voltage; 489 /* Type of MMC */ 490 enum sdmmc_device_mode cdn_sdmmc_dev_type; 491 }; 492 493 /*descriptor structure with 8 byte alignment*/ 494 struct sdhc_cdns_desc { 495 /* 8 bit attribute */ 496 uint8_t attr; 497 /* reserved bits in desc */ 498 uint8_t reserved; 499 /* page length for the descriptor */ 500 uint16_t len; 501 /* lower 32 bits for buffer (64 bit addressing) */ 502 uint32_t addr_lo; 503 /* higher 32 bits for buffer (64 bit addressing) */ 504 uint32_t addr_hi; 505 } __aligned(8); 506 507 void sdhc_cdns_sdmmc_init(struct sdhc_cdns_params *params, struct sdmmc_device_info *info, 508 const struct sdhc_cdns_ops **cb_sdmmc_ops); 509
