1 /*
2 * Copyright 2017, 2024 NXP
3 * Copyright (c) 2020-2021 Vestas Wind Systems A/S
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT nxp_kinetis_ftm_pwm
9
10 #include <zephyr/drivers/clock_control.h>
11 #include <errno.h>
12 #include <zephyr/drivers/pwm.h>
13 #include <zephyr/irq.h>
14 #include <soc.h>
15 #include <fsl_ftm.h>
16 #include <fsl_clock.h>
17 #include <zephyr/drivers/pinctrl.h>
18
19 #include <zephyr/logging/log.h>
20
21 LOG_MODULE_REGISTER(pwm_mcux_ftm, CONFIG_PWM_LOG_LEVEL);
22
23 #define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)
24
25 /* PWM capture operates on channel pairs */
26 #define MAX_CAPTURE_PAIRS (MAX_CHANNELS / 2U)
27 #define PAIR_1ST_CH(pair) (pair * 2U)
28 #define PAIR_2ND_CH(pair) (PAIR_1ST_CH(pair) + 1)
29
30 struct mcux_ftm_config {
31 FTM_Type *base;
32 const struct device *clock_dev;
33 clock_control_subsys_t clock_subsys;
34 ftm_clock_source_t ftm_clock_source;
35 ftm_clock_prescale_t prescale;
36 uint8_t channel_count;
37 ftm_pwm_mode_t mode;
38 #ifdef CONFIG_PWM_CAPTURE
39 void (*irq_config_func)(const struct device *dev);
40 #endif /* CONFIG_PWM_CAPTURE */
41 const struct pinctrl_dev_config *pincfg;
42 };
43
44 struct mcux_ftm_capture_data {
45 ftm_dual_edge_capture_param_t param;
46 pwm_capture_callback_handler_t callback;
47 void *user_data;
48 uint32_t first_edge_overflows;
49 uint16_t first_edge_cnt;
50 bool first_edge_overflow;
51 bool pulse_capture;
52 };
53
54 struct mcux_ftm_data {
55 uint32_t clock_freq;
56 uint32_t period_cycles;
57 ftm_chnl_pwm_config_param_t channel[MAX_CHANNELS];
58 #ifdef CONFIG_PWM_CAPTURE
59 uint32_t overflows;
60 struct mcux_ftm_capture_data capture[MAX_CAPTURE_PAIRS];
61 #endif /* CONFIG_PWM_CAPTURE */
62 };
63
mcux_ftm_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)64 static int mcux_ftm_set_cycles(const struct device *dev, uint32_t channel,
65 uint32_t period_cycles, uint32_t pulse_cycles,
66 pwm_flags_t flags)
67 {
68 const struct mcux_ftm_config *config = dev->config;
69 struct mcux_ftm_data *data = dev->data;
70 status_t status;
71 #ifdef CONFIG_PWM_CAPTURE
72 uint32_t pair = channel / 2U;
73 uint32_t irqs;
74 #endif /* CONFIG_PWM_CAPTURE */
75
76 if (period_cycles == 0U) {
77 LOG_ERR("Channel can not be set to inactive level");
78 return -ENOTSUP;
79 }
80
81 if (period_cycles > UINT16_MAX) {
82 LOG_ERR("Period cycles must be less or equal than %u", UINT16_MAX);
83 return -EINVAL;
84 }
85
86 if (channel >= config->channel_count) {
87 LOG_ERR("Invalid channel");
88 return -ENOTSUP;
89 }
90
91 #ifdef CONFIG_PWM_CAPTURE
92 irqs = FTM_GetEnabledInterrupts(config->base);
93 if (irqs & BIT(PAIR_2ND_CH(pair))) {
94 LOG_ERR("Cannot set PWM, capture in progress on pair %d", pair);
95 return -EBUSY;
96 }
97 #endif /* CONFIG_PWM_CAPTURE */
98
99 data->channel[channel].dutyValue = pulse_cycles;
100
101 if ((flags & PWM_POLARITY_INVERTED) == 0) {
102 data->channel[channel].level = kFTM_HighTrue;
103 } else {
104 data->channel[channel].level = kFTM_LowTrue;
105 }
106
107 LOG_DBG("pulse_cycles=%d, period_cycles=%d, flags=%d",
108 pulse_cycles, period_cycles, flags);
109
110 if (period_cycles != data->period_cycles) {
111 #ifdef CONFIG_PWM_CAPTURE
112 if (irqs & BIT_MASK(ARRAY_SIZE(data->channel))) {
113 LOG_ERR("Cannot change period, capture in progress");
114 return -EBUSY;
115 }
116 #endif /* CONFIG_PWM_CAPTURE */
117
118 if (data->period_cycles != 0) {
119 /* Only warn when not changing from zero */
120 LOG_WRN("Changing period cycles from %d to %d"
121 " affects all %d channels in %s",
122 data->period_cycles, period_cycles,
123 config->channel_count, dev->name);
124 }
125
126 data->period_cycles = period_cycles;
127
128 FTM_StopTimer(config->base);
129 FTM_SetTimerPeriod(config->base, period_cycles);
130
131 FTM_SetSoftwareTrigger(config->base, true);
132 FTM_StartTimer(config->base, config->ftm_clock_source);
133 }
134
135 status = FTM_SetupPwmMode(config->base, data->channel,
136 config->channel_count, config->mode);
137 if (status != kStatus_Success) {
138 LOG_ERR("Could not set up pwm");
139 return -ENOTSUP;
140 }
141 FTM_SetSoftwareTrigger(config->base, true);
142
143 return 0;
144 }
145
146 #ifdef CONFIG_PWM_CAPTURE
mcux_ftm_configure_capture(const struct device * dev,uint32_t channel,pwm_flags_t flags,pwm_capture_callback_handler_t cb,void * user_data)147 static int mcux_ftm_configure_capture(const struct device *dev,
148 uint32_t channel, pwm_flags_t flags,
149 pwm_capture_callback_handler_t cb,
150 void *user_data)
151 {
152 const struct mcux_ftm_config *config = dev->config;
153 struct mcux_ftm_data *data = dev->data;
154 ftm_dual_edge_capture_param_t *param;
155 uint32_t pair = channel / 2U;
156
157 if (channel & 0x1U) {
158 LOG_ERR("PWM capture only supported on even channels");
159 return -ENOTSUP;
160 }
161
162 if (pair >= ARRAY_SIZE(data->capture)) {
163 LOG_ERR("Invalid channel pair %d", pair);
164 return -EINVAL;
165 }
166
167 if (FTM_GetEnabledInterrupts(config->base) & BIT(PAIR_2ND_CH(pair))) {
168 LOG_ERR("Capture already active on channel pair %d", pair);
169 return -EBUSY;
170 }
171
172 if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
173 LOG_ERR("No capture type specified");
174 return -EINVAL;
175 }
176
177 if ((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_BOTH) {
178 LOG_ERR("Cannot capture both period and pulse width");
179 return -ENOTSUP;
180 }
181
182 data->capture[pair].callback = cb;
183 data->capture[pair].user_data = user_data;
184 param = &data->capture[pair].param;
185
186 if ((flags & PWM_CAPTURE_MODE_MASK) == PWM_CAPTURE_MODE_CONTINUOUS) {
187 param->mode = kFTM_Continuous;
188 } else {
189 param->mode = kFTM_OneShot;
190 }
191
192 if (flags & PWM_CAPTURE_TYPE_PERIOD) {
193 data->capture[pair].pulse_capture = false;
194
195 if (flags & PWM_POLARITY_INVERTED) {
196 param->currChanEdgeMode = kFTM_FallingEdge;
197 param->nextChanEdgeMode = kFTM_FallingEdge;
198 } else {
199 param->currChanEdgeMode = kFTM_RisingEdge;
200 param->nextChanEdgeMode = kFTM_RisingEdge;
201 }
202 } else {
203 data->capture[pair].pulse_capture = true;
204
205 if (flags & PWM_POLARITY_INVERTED) {
206 param->currChanEdgeMode = kFTM_FallingEdge;
207 param->nextChanEdgeMode = kFTM_RisingEdge;
208 } else {
209 param->currChanEdgeMode = kFTM_RisingEdge;
210 param->nextChanEdgeMode = kFTM_FallingEdge;
211 }
212 }
213
214 return 0;
215 }
216
mcux_ftm_enable_capture(const struct device * dev,uint32_t channel)217 static int mcux_ftm_enable_capture(const struct device *dev, uint32_t channel)
218 {
219 const struct mcux_ftm_config *config = dev->config;
220 struct mcux_ftm_data *data = dev->data;
221 uint32_t pair = channel / 2U;
222
223 if (channel & 0x1U) {
224 LOG_ERR("PWM capture only supported on even channels");
225 return -ENOTSUP;
226 }
227
228 if (pair >= ARRAY_SIZE(data->capture)) {
229 LOG_ERR("Invalid channel pair %d", pair);
230 return -EINVAL;
231 }
232
233 if (!data->capture[pair].callback) {
234 LOG_ERR("PWM capture not configured");
235 return -EINVAL;
236 }
237
238 if (FTM_GetEnabledInterrupts(config->base) & BIT(PAIR_2ND_CH(pair))) {
239 LOG_ERR("Capture already active on channel pair %d", pair);
240 return -EBUSY;
241 }
242
243 FTM_ClearStatusFlags(config->base, BIT(PAIR_1ST_CH(pair)) |
244 BIT(PAIR_2ND_CH(pair)));
245
246 FTM_SetupDualEdgeCapture(config->base, pair, &data->capture[pair].param,
247 CONFIG_PWM_CAPTURE_MCUX_FTM_FILTER_VALUE);
248
249 FTM_EnableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)) |
250 BIT(PAIR_2ND_CH(pair)));
251
252 return 0;
253 }
254
mcux_ftm_disable_capture(const struct device * dev,uint32_t channel)255 static int mcux_ftm_disable_capture(const struct device *dev, uint32_t channel)
256 {
257 const struct mcux_ftm_config *config = dev->config;
258 struct mcux_ftm_data *data = dev->data;
259 uint32_t pair = channel / 2U;
260
261 if (channel & 0x1U) {
262 LOG_ERR("PWM capture only supported on even channels");
263 return -ENOTSUP;
264 }
265
266 if (pair >= ARRAY_SIZE(data->capture)) {
267 LOG_ERR("Invalid channel pair %d", pair);
268 return -EINVAL;
269 }
270
271 FTM_DisableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)) |
272 BIT(PAIR_2ND_CH(pair)));
273
274 /* Clear Dual Edge Capture Enable bit */
275 config->base->COMBINE &= ~(1UL << (FTM_COMBINE_DECAP0_SHIFT +
276 (FTM_COMBINE_COMBINE1_SHIFT * pair)));
277
278 return 0;
279 }
280
mcux_ftm_capture_first_edge(const struct device * dev,uint32_t channel,uint16_t cnt,bool overflow)281 static void mcux_ftm_capture_first_edge(const struct device *dev, uint32_t channel,
282 uint16_t cnt, bool overflow)
283 {
284 const struct mcux_ftm_config *config = dev->config;
285 struct mcux_ftm_data *data = dev->data;
286 struct mcux_ftm_capture_data *capture;
287 uint32_t pair = channel / 2U;
288
289 __ASSERT_NO_MSG(pair < ARRAY_SIZE(data->capture));
290 capture = &data->capture[pair];
291
292 FTM_DisableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)));
293
294 capture->first_edge_cnt = cnt;
295 capture->first_edge_overflows = data->overflows;
296 capture->first_edge_overflow = overflow;
297
298 LOG_DBG("pair = %d, 1st cnt = %u, 1st ovf = %d", pair, cnt, overflow);
299 }
300
mcux_ftm_capture_second_edge(const struct device * dev,uint32_t channel,uint16_t cnt,bool overflow)301 static void mcux_ftm_capture_second_edge(const struct device *dev, uint32_t channel,
302 uint16_t cnt, bool overflow)
303
304 {
305 const struct mcux_ftm_config *config = dev->config;
306 struct mcux_ftm_data *data = dev->data;
307 uint32_t second_edge_overflows = data->overflows;
308 struct mcux_ftm_capture_data *capture;
309 uint32_t pair = channel / 2U;
310 uint32_t overflows;
311 uint32_t first_cnv;
312 uint32_t second_cnv;
313 uint32_t cycles = 0;
314 int status = 0;
315
316 __ASSERT_NO_MSG(pair < ARRAY_SIZE(data->capture));
317 capture = &data->capture[pair];
318
319 first_cnv = config->base->CONTROLS[PAIR_1ST_CH(pair)].CnV;
320 second_cnv = config->base->CONTROLS[PAIR_2ND_CH(pair)].CnV;
321
322 if (capture->pulse_capture) {
323 /* Clear both edge flags for pulse capture to capture first edge overflow counter */
324 FTM_ClearStatusFlags(config->base, BIT(PAIR_1ST_CH(pair)) | BIT(PAIR_2ND_CH(pair)));
325 } else {
326 /* Only clear second edge flag for period capture as next first edge is this edge */
327 FTM_ClearStatusFlags(config->base, BIT(PAIR_2ND_CH(pair)));
328 }
329
330 if (unlikely(capture->first_edge_overflow && first_cnv > capture->first_edge_cnt)) {
331 /* Compensate for the overflow registered in the same IRQ */
332 capture->first_edge_overflows--;
333 }
334
335 if (unlikely(overflow && second_cnv > cnt)) {
336 /* Compensate for the overflow registered in the same IRQ */
337 second_edge_overflows--;
338 }
339
340 overflows = second_edge_overflows - capture->first_edge_overflows;
341
342 /* Calculate cycles, check for overflows */
343 if (overflows > 0) {
344 if (u32_mul_overflow(overflows, config->base->MOD, &cycles)) {
345 LOG_ERR("overflow while calculating cycles");
346 status = -ERANGE;
347 } else {
348 cycles -= first_cnv;
349 if (u32_add_overflow(cycles, second_cnv, &cycles)) {
350 LOG_ERR("overflow while calculating cycles");
351 cycles = 0;
352 status = -ERANGE;
353 }
354 }
355 } else {
356 cycles = second_cnv - first_cnv;
357 }
358
359 LOG_DBG("pair = %d, 1st ovfs = %u, 2nd ovfs = %u, ovfs = %u, 1st cnv = %u, "
360 "2nd cnv = %u, cycles = %u, 2nd cnt = %u, 2nd ovf = %d",
361 pair, capture->first_edge_overflows, second_edge_overflows, overflows, first_cnv,
362 second_cnv, cycles, cnt, overflow);
363
364 if (capture->pulse_capture) {
365 capture->callback(dev, pair, 0, cycles, status,
366 capture->user_data);
367 } else {
368 capture->callback(dev, pair, cycles, 0, status,
369 capture->user_data);
370 }
371
372 if (capture->param.mode == kFTM_OneShot) {
373 /* One-shot capture done */
374 FTM_DisableInterrupts(config->base, BIT(PAIR_2ND_CH(pair)));
375 } else if (capture->pulse_capture) {
376 /* Prepare for first edge of next pulse capture */
377 FTM_EnableInterrupts(config->base, BIT(PAIR_1ST_CH(pair)));
378 } else {
379 /* First edge of next period capture is second edge of this capture (this edge) */
380 capture->first_edge_cnt = cnt;
381 capture->first_edge_overflows = second_edge_overflows;
382 capture->first_edge_overflow = false;
383 }
384 }
385
mcux_ftm_handle_overflow(const struct device * dev)386 static bool mcux_ftm_handle_overflow(const struct device *dev)
387 {
388 const struct mcux_ftm_config *config = dev->config;
389 struct mcux_ftm_data *data = dev->data;
390
391 if (FTM_GetStatusFlags(config->base) & kFTM_TimeOverflowFlag) {
392 data->overflows++;
393 FTM_ClearStatusFlags(config->base, kFTM_TimeOverflowFlag);
394 return true;
395 }
396
397 return false;
398 }
399
mcux_ftm_irq_handler(const struct device * dev,uint32_t chan_start,uint32_t chan_end)400 static void mcux_ftm_irq_handler(const struct device *dev, uint32_t chan_start, uint32_t chan_end)
401 {
402 const struct mcux_ftm_config *config = dev->config;
403 bool overflow;
404 uint32_t flags;
405 uint32_t irqs;
406 uint16_t cnt;
407 uint32_t ch;
408
409 flags = FTM_GetStatusFlags(config->base);
410 irqs = FTM_GetEnabledInterrupts(config->base);
411 cnt = config->base->CNT;
412
413 overflow = mcux_ftm_handle_overflow(dev);
414
415 for (ch = chan_start; ch < chan_end; ch++) {
416 if ((flags & BIT(ch)) && (irqs & BIT(ch))) {
417 if (ch & 1) {
418 mcux_ftm_capture_second_edge(dev, ch, cnt, overflow);
419 } else {
420 mcux_ftm_capture_first_edge(dev, ch, cnt, overflow);
421 }
422 }
423 }
424 }
425 #endif /* CONFIG_PWM_CAPTURE */
426
mcux_ftm_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)427 static int mcux_ftm_get_cycles_per_sec(const struct device *dev,
428 uint32_t channel, uint64_t *cycles)
429 {
430 const struct mcux_ftm_config *config = dev->config;
431 struct mcux_ftm_data *data = dev->data;
432
433 *cycles = data->clock_freq >> config->prescale;
434
435 return 0;
436 }
437
mcux_ftm_init(const struct device * dev)438 static int mcux_ftm_init(const struct device *dev)
439 {
440 const struct mcux_ftm_config *config = dev->config;
441 struct mcux_ftm_data *data = dev->data;
442 ftm_chnl_pwm_config_param_t *channel = data->channel;
443 ftm_config_t ftm_config;
444 int i;
445 int err;
446
447 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
448 if (err != 0) {
449 return err;
450 }
451
452 if (config->channel_count > ARRAY_SIZE(data->channel)) {
453 LOG_ERR("Invalid channel count");
454 return -EINVAL;
455 }
456
457 if (!device_is_ready(config->clock_dev)) {
458 LOG_ERR("clock control device not ready");
459 return -ENODEV;
460 }
461
462 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
463 &data->clock_freq)) {
464 LOG_ERR("Could not get clock frequency");
465 return -EINVAL;
466 }
467
468 for (i = 0; i < config->channel_count; i++) {
469 channel->chnlNumber = i;
470 channel->level = kFTM_NoPwmSignal;
471 channel->dutyValue = 0;
472 channel->firstEdgeValue = 0;
473 channel++;
474 }
475
476 FTM_GetDefaultConfig(&ftm_config);
477 ftm_config.prescale = config->prescale;
478
479 FTM_Init(config->base, &ftm_config);
480
481 #ifdef CONFIG_PWM_CAPTURE
482 config->irq_config_func(dev);
483 FTM_EnableInterrupts(config->base,
484 kFTM_TimeOverflowInterruptEnable);
485
486 data->period_cycles = 0xFFFFU;
487 FTM_SetTimerPeriod(config->base, data->period_cycles);
488 FTM_SetSoftwareTrigger(config->base, true);
489 FTM_StartTimer(config->base, config->ftm_clock_source);
490 #endif /* CONFIG_PWM_CAPTURE */
491
492 return 0;
493 }
494
495 static const struct pwm_driver_api mcux_ftm_driver_api = {
496 .set_cycles = mcux_ftm_set_cycles,
497 .get_cycles_per_sec = mcux_ftm_get_cycles_per_sec,
498 #ifdef CONFIG_PWM_CAPTURE
499 .configure_capture = mcux_ftm_configure_capture,
500 .enable_capture = mcux_ftm_enable_capture,
501 .disable_capture = mcux_ftm_disable_capture,
502 #endif /* CONFIG_PWM_CAPTURE */
503 };
504
505 #define TO_FTM_PRESCALE_DIVIDE(val) _DO_CONCAT(kFTM_Prescale_Divide_, val)
506
507 #ifdef CONFIG_PWM_CAPTURE
508 #if IS_EQ(DT_NUM_IRQS(DT_DRV_INST(0)), 1)
mcux_ftm_isr(const struct device * dev)509 static void mcux_ftm_isr(const struct device *dev)
510 {
511 const struct mcux_ftm_config *cfg = dev->config;
512
513 mcux_ftm_irq_handler(dev, 0, cfg->channel_count);
514 }
515
516 #define FTM_CONFIG_FUNC(n) \
517 static void mcux_ftm_config_func_##n(const struct device *dev) \
518 { \
519 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
520 mcux_ftm_isr, DEVICE_DT_INST_GET(n), 0); \
521 irq_enable(DT_INST_IRQN(n)); \
522 }
523 #else /* Multiple interrupts */
524 #define FTM_ISR_FUNC_NAME(suffix) _DO_CONCAT(mcux_ftm_isr_, suffix)
525 #define FTM_ISR_FUNC(chan_start, chan_end) \
526 static void mcux_ftm_isr_##chan_start##_##chan_end(const struct device *dev) \
527 { \
528 mcux_ftm_irq_handler(dev, chan_start, chan_end + 1); \
529 }
530
531 #define FTM_ISR_CONFIG(node_id, prop, idx) \
532 do { \
533 IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), \
534 DT_IRQ_BY_IDX(node_id, idx, priority), \
535 FTM_ISR_FUNC_NAME(DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)), \
536 DEVICE_DT_GET(node_id), \
537 0); \
538 irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq)); \
539 } while (false);
540
541 #define FTM_CONFIG_FUNC(n) \
542 static void mcux_ftm_config_func_##n(const struct device *dev) \
543 { \
544 DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, FTM_ISR_CONFIG) \
545 }
546
547 #if DT_INST_IRQ_HAS_NAME(0, overflow)
mcux_ftm_isr_overflow(const struct device * dev)548 static void mcux_ftm_isr_overflow(const struct device *dev)
549 {
550 mcux_ftm_handle_overflow(dev);
551 }
552 #endif
553 #if DT_INST_IRQ_HAS_NAME(0, 0_1)
554 FTM_ISR_FUNC(0, 1)
555 #endif
556 #if DT_INST_IRQ_HAS_NAME(0, 2_3)
557 FTM_ISR_FUNC(2, 3)
558 #endif
559 #if DT_INST_IRQ_HAS_NAME(0, 4_5)
560 FTM_ISR_FUNC(4, 5)
561 #endif
562 #if DT_INST_IRQ_HAS_NAME(0, 6_7)
563 FTM_ISR_FUNC(6, 7)
564 #endif
565 #endif /* IS_EQ(DT_NUM_IRQS(DT_DRV_INST(0)), 1) */
566 #define FTM_CFG_CAPTURE_INIT(n) \
567 .irq_config_func = mcux_ftm_config_func_##n
568 #define FTM_INIT_CFG(n) FTM_DECLARE_CFG(n, FTM_CFG_CAPTURE_INIT(n))
569 #else /* !CONFIG_PWM_CAPTURE */
570 #define FTM_CONFIG_FUNC(n)
571 #define FTM_CFG_CAPTURE_INIT
572 #define FTM_INIT_CFG(n) FTM_DECLARE_CFG(n, FTM_CFG_CAPTURE_INIT)
573 #endif /* !CONFIG_PWM_CAPTURE */
574
575 #define FTM_DECLARE_CFG(n, CAPTURE_INIT) \
576 static const struct mcux_ftm_config mcux_ftm_config_##n = { \
577 .base = (FTM_Type *)DT_INST_REG_ADDR(n),\
578 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
579 .clock_subsys = (clock_control_subsys_t) \
580 DT_INST_CLOCKS_CELL(n, name), \
581 .ftm_clock_source = (ftm_clock_source_t)(DT_INST_ENUM_IDX(n, clock_source) + 1U), \
582 .prescale = TO_FTM_PRESCALE_DIVIDE(DT_INST_PROP(n, prescaler)),\
583 .channel_count = FSL_FEATURE_FTM_CHANNEL_COUNTn((FTM_Type *) \
584 DT_INST_REG_ADDR(n)), \
585 .mode = kFTM_EdgeAlignedPwm, \
586 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
587 CAPTURE_INIT \
588 }
589
590 #define FTM_DEVICE(n) \
591 PINCTRL_DT_INST_DEFINE(n); \
592 static struct mcux_ftm_data mcux_ftm_data_##n; \
593 static const struct mcux_ftm_config mcux_ftm_config_##n; \
594 DEVICE_DT_INST_DEFINE(n, &mcux_ftm_init, \
595 NULL, &mcux_ftm_data_##n, \
596 &mcux_ftm_config_##n, \
597 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
598 &mcux_ftm_driver_api); \
599 FTM_CONFIG_FUNC(n) \
600 FTM_INIT_CFG(n);
601
602 DT_INST_FOREACH_STATUS_OKAY(FTM_DEVICE)
603
