1 /*
2 * Copyright (c) 2022, Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_smartbond_gpio
8
9 #include <zephyr/drivers/gpio/gpio_utils.h>
10
11 #include <stdint.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/irq.h>
14 #include <zephyr/pm/device.h>
15
16 #include <DA1469xAB.h>
17 #include <da1469x_pdc.h>
18 #include <da1469x_pd.h>
19
20 #define GPIO_MODE_RESET 0x200
21
22 #define GPIO_PUPD_INPUT 0
23 #define GPIO_PUPD_INPUT_PU 1
24 #define GPIO_PUPD_INPUT_PD 2
25 #define GPIO_PUPD_OUTPUT 3
26
27 /* GPIO P0 and P1 share single GPIO and WKUP peripheral instance with separate
28 * set registers for P0 and P1 interleaved. The starting registers for direct
29 * data access, bit access, mode, latch and wake-up controller are defined in
30 * device tree.
31 */
32
33 struct gpio_smartbond_data_regs {
34 uint32_t data;
35 uint32_t _reserved0;
36 uint32_t set;
37 uint32_t _reserved1;
38 uint32_t reset;
39 };
40
41 struct gpio_smartbond_latch_regs {
42 uint32_t latch;
43 uint32_t set;
44 uint32_t reset;
45 };
46
47 struct gpio_smartbond_wkup_regs {
48 uint32_t select;
49 uint32_t _reserved0[4];
50 uint32_t pol;
51 uint32_t _reserved1[4];
52 uint32_t status;
53 uint32_t _reserved2[2];
54 uint32_t clear;
55 uint32_t _reserved3[2];
56 uint32_t sel;
57 };
58
59 struct gpio_smartbond_data {
60 /* gpio_driver_data needs to be first */
61 struct gpio_driver_data common;
62 /* Pins that are configured for both edges (handled by software) */
63 gpio_port_pins_t both_edges_pins;
64 sys_slist_t callbacks;
65 #if CONFIG_PM_DEVICE
66 /*
67 * Saved state consist of:
68 * 1 word for GPIO output port state
69 * GPIOx_NGPIOS words for each pin mode
70 */
71 uint32_t *gpio_saved_state;
72 #endif
73 };
74
75 struct gpio_smartbond_config {
76 /* gpio_driver_config needs to be first */
77 struct gpio_driver_config common;
78 volatile struct gpio_smartbond_data_regs *data_regs;
79 volatile uint32_t *mode_regs;
80 volatile struct gpio_smartbond_latch_regs *latch_regs;
81 volatile struct gpio_smartbond_wkup_regs *wkup_regs;
82 /* Value of TRIG_SELECT for PDC_CTRLx_REG entry */
83 uint8_t wkup_trig_select;
84 #if CONFIG_PM_DEVICE
85 uint8_t ngpios;
86 #endif
87 };
88
gpio_smartbond_wkup_init(void)89 static void gpio_smartbond_wkup_init(void)
90 {
91 static bool wkup_init;
92
93 /* Wakeup controller is shared for both GPIO ports and should
94 * be initialized only once.
95 */
96 if (!wkup_init) {
97 WAKEUP->WKUP_CTRL_REG = 0;
98 WAKEUP->WKUP_CLEAR_P0_REG = 0xffffffff;
99 WAKEUP->WKUP_CLEAR_P1_REG = 0xffffffff;
100 WAKEUP->WKUP_SELECT_P0_REG = 0;
101 WAKEUP->WKUP_SELECT_P1_REG = 0;
102 WAKEUP->WKUP_SEL_GPIO_P0_REG = 0;
103 WAKEUP->WKUP_SEL_GPIO_P1_REG = 0;
104 WAKEUP->WKUP_RESET_IRQ_REG = 0;
105
106 CRG_TOP->CLK_TMR_REG |= CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk;
107
108 WAKEUP->WKUP_CTRL_REG = WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk;
109
110 wkup_init = true;
111 }
112 }
113
gpio_smartbond_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)114 static int gpio_smartbond_pin_configure(const struct device *dev,
115 gpio_pin_t pin, gpio_flags_t flags)
116 {
117 const struct gpio_smartbond_config *config = dev->config;
118
119 if (flags == GPIO_DISCONNECTED) {
120 /* Reset to default value */
121 config->mode_regs[pin] = GPIO_MODE_RESET;
122 return 0;
123 }
124
125 if ((flags & GPIO_INPUT) && (flags & GPIO_OUTPUT)) {
126 /* Simultaneous in/out is not supported */
127 return -ENOTSUP;
128 }
129
130 if (flags & GPIO_OUTPUT) {
131 config->mode_regs[pin] = GPIO_PUPD_OUTPUT << GPIO_P0_00_MODE_REG_PUPD_Pos;
132
133 if (flags & GPIO_OUTPUT_INIT_LOW) {
134 config->data_regs->reset = BIT(pin);
135 } else if (flags & GPIO_OUTPUT_INIT_HIGH) {
136 config->data_regs->set = BIT(pin);
137 }
138
139 return 0;
140 }
141
142 if (flags & GPIO_PULL_DOWN) {
143 config->mode_regs[pin] = GPIO_PUPD_INPUT_PD << GPIO_P0_00_MODE_REG_PUPD_Pos;
144 } else if (flags & GPIO_PULL_UP) {
145 config->mode_regs[pin] = GPIO_PUPD_INPUT_PU << GPIO_P0_00_MODE_REG_PUPD_Pos;
146 } else {
147 config->mode_regs[pin] = GPIO_PUPD_INPUT << GPIO_P0_00_MODE_REG_PUPD_Pos;
148 }
149
150 return 0;
151 }
152
gpio_smartbond_port_get_raw(const struct device * dev,gpio_port_value_t * value)153 static int gpio_smartbond_port_get_raw(const struct device *dev,
154 gpio_port_value_t *value)
155 {
156 const struct gpio_smartbond_config *config = dev->config;
157
158 *value = config->data_regs->data;
159
160 return 0;
161 }
162
gpio_smartbond_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)163 static int gpio_smartbond_port_set_masked_raw(const struct device *dev,
164 gpio_port_pins_t mask,
165 gpio_port_value_t value)
166 {
167 const struct gpio_smartbond_config *config = dev->config;
168
169 config->data_regs->data = value & mask;
170
171 return 0;
172 }
173
gpio_smartbond_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)174 static int gpio_smartbond_port_set_bits_raw(const struct device *dev,
175 gpio_port_pins_t pins)
176 {
177 const struct gpio_smartbond_config *config = dev->config;
178
179 config->data_regs->set = pins;
180
181 return 0;
182 }
183
gpio_smartbond_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)184 static int gpio_smartbond_port_clear_bits_raw(const struct device *dev,
185 gpio_port_pins_t pins)
186 {
187 const struct gpio_smartbond_config *config = dev->config;
188
189 config->data_regs->reset = pins;
190
191 return 0;
192 }
193
gpio_smartbond_port_toggle_bits(const struct device * dev,gpio_port_pins_t mask)194 static int gpio_smartbond_port_toggle_bits(const struct device *dev,
195 gpio_port_pins_t mask)
196 {
197 const struct gpio_smartbond_config *config = dev->config;
198 volatile uint32_t *reg = &config->data_regs->data;
199
200 *reg = *reg ^ mask;
201
202 return 0;
203 }
204
gpio_smartbond_arm_next_edge_interrupt(const struct device * dev,uint32_t pin_mask)205 static void gpio_smartbond_arm_next_edge_interrupt(const struct device *dev,
206 uint32_t pin_mask)
207 {
208 const struct gpio_smartbond_config *config = dev->config;
209 uint32_t pin_value;
210
211 do {
212 pin_value = config->data_regs->data & pin_mask;
213 if (pin_value) {
214 config->wkup_regs->pol |= pin_mask;
215 } else {
216 config->wkup_regs->pol &= ~pin_mask;
217 }
218 } while (pin_value != (config->data_regs->data & pin_mask));
219 }
220
gpio_smartbond_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)221 static int gpio_smartbond_pin_interrupt_configure(const struct device *dev,
222 gpio_pin_t pin,
223 enum gpio_int_mode mode,
224 enum gpio_int_trig trig)
225 {
226 const struct gpio_smartbond_config *config = dev->config;
227 struct gpio_smartbond_data *data = dev->data;
228 uint32_t pin_mask = BIT(pin);
229 #if CONFIG_PM
230 int trig_select_id = (config->wkup_trig_select << 5) | pin;
231 int pdc_ix;
232 #endif
233
234 /* Not supported by hardware */
235 if (mode == GPIO_INT_MODE_LEVEL) {
236 return -ENOTSUP;
237 }
238
239 #if CONFIG_PM
240 pdc_ix = da1469x_pdc_find(trig_select_id, MCU_PDC_MASTER_M33, MCU_PDC_EN_XTAL);
241 #endif
242 if (mode == GPIO_INT_MODE_DISABLED) {
243 config->wkup_regs->sel &= ~pin_mask;
244 config->wkup_regs->clear = pin_mask;
245 data->both_edges_pins &= ~pin_mask;
246 #if CONFIG_PM
247 da1469x_pdc_del(pdc_ix);
248 #endif
249 } else {
250 if (trig == GPIO_INT_TRIG_BOTH) {
251 /* Not supported by hardware */
252 data->both_edges_pins |= pin_mask;
253 gpio_smartbond_arm_next_edge_interrupt(dev, pin_mask);
254 } else if (trig == GPIO_INT_TRIG_HIGH) {
255 config->wkup_regs->pol &= ~pin_mask;
256 } else {
257 config->wkup_regs->pol |= pin_mask;
258 }
259
260 config->wkup_regs->sel |= pin_mask;
261 #if CONFIG_PM
262 if (pdc_ix < 0) {
263 pdc_ix = da1469x_pdc_add(trig_select_id, MCU_PDC_MASTER_M33,
264 MCU_PDC_EN_XTAL);
265 }
266 if (pdc_ix < 0) {
267 return -ENOMEM;
268 }
269 #endif
270 }
271
272 return 0;
273 }
274
gpio_smartbond_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)275 static int gpio_smartbond_manage_callback(const struct device *dev,
276 struct gpio_callback *callback, bool set)
277 {
278 struct gpio_smartbond_data *data = dev->data;
279
280 return gpio_manage_callback(&data->callbacks, callback, set);
281 }
282
gpio_smartbond_isr(const struct device * dev)283 static void gpio_smartbond_isr(const struct device *dev)
284 {
285 const struct gpio_smartbond_config *config = dev->config;
286 struct gpio_smartbond_data *data = dev->data;
287 uint32_t stat;
288 uint32_t two_edge_triggered;
289
290 WAKEUP->WKUP_RESET_IRQ_REG = WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk;
291
292 stat = config->wkup_regs->status;
293
294 two_edge_triggered = stat & data->both_edges_pins;
295 while (two_edge_triggered) {
296 int pos = find_lsb_set(two_edge_triggered) - 1;
297
298 two_edge_triggered &= ~BIT(pos);
299 /* Re-arm for other edge */
300 gpio_smartbond_arm_next_edge_interrupt(dev, BIT(pos));
301 }
302
303 config->wkup_regs->clear = stat;
304
305 gpio_fire_callbacks(&data->callbacks, dev, stat);
306 }
307
308 #ifdef CONFIG_PM_DEVICE
309
gpio_latch_inst(mem_addr_t data_reg,mem_addr_t mode_reg,mem_addr_t latch_reg,uint8_t ngpios,uint32_t * data,uint32_t * mode)310 static void gpio_latch_inst(mem_addr_t data_reg, mem_addr_t mode_reg, mem_addr_t latch_reg,
311 uint8_t ngpios, uint32_t *data, uint32_t *mode)
312 {
313 uint8_t idx;
314
315 *data = sys_read32(data_reg);
316 for (idx = 0; idx < ngpios; idx++, mode_reg += 4) {
317 mode[idx] = sys_read32(mode_reg);
318 }
319 sys_write32(BIT_MASK(ngpios), latch_reg);
320
321 }
322
gpio_unlatch_inst(mem_addr_t data_reg,mem_addr_t mode_reg,mem_addr_t latch_reg,uint8_t ngpios,uint32_t data,uint32_t * mode)323 static void gpio_unlatch_inst(mem_addr_t data_reg, mem_addr_t mode_reg, mem_addr_t latch_reg,
324 uint8_t ngpios, uint32_t data, uint32_t *mode)
325 {
326 uint8_t idx;
327
328 sys_write32(data, data_reg);
329 for (idx = 0; idx < ngpios; idx++, mode_reg += 4) {
330 sys_write32(mode[idx], mode_reg);
331 }
332 sys_write32(BIT_MASK(ngpios), latch_reg);
333 }
334
gpio_latch(const struct device * dev)335 static void gpio_latch(const struct device *dev)
336 {
337 const struct gpio_smartbond_config *config = dev->config;
338 const struct gpio_smartbond_data *data = dev->data;
339
340 gpio_latch_inst((mem_addr_t)&config->data_regs->data,
341 (mem_addr_t)config->mode_regs,
342 (mem_addr_t)&config->latch_regs->reset,
343 config->ngpios, data->gpio_saved_state, data->gpio_saved_state + 1);
344 }
345
gpio_unlatch(const struct device * dev)346 static void gpio_unlatch(const struct device *dev)
347 {
348 const struct gpio_smartbond_config *config = dev->config;
349 const struct gpio_smartbond_data *data = dev->data;
350
351 gpio_unlatch_inst((mem_addr_t)&config->data_regs->data,
352 (mem_addr_t)config->mode_regs,
353 (mem_addr_t)&config->latch_regs->set,
354 config->ngpios, data->gpio_saved_state[0], data->gpio_saved_state + 1);
355 }
356
gpio_smartbond_pm_action(const struct device * dev,enum pm_device_action action)357 static int gpio_smartbond_pm_action(const struct device *dev,
358 enum pm_device_action action)
359 {
360 int ret = 0;
361
362 switch (action) {
363 case PM_DEVICE_ACTION_RESUME:
364 da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
365 gpio_unlatch(dev);
366 break;
367 case PM_DEVICE_ACTION_SUSPEND:
368 gpio_latch(dev);
369 da1469x_pd_release(MCU_PD_DOMAIN_COM);
370 break;
371 default:
372 ret = -ENOTSUP;
373 }
374
375 return ret;
376 }
377
378 #endif /* CONFIG_PM_DEVICE */
379
380 /* GPIO driver registration */
381 static const struct gpio_driver_api gpio_smartbond_drv_api_funcs = {
382 .pin_configure = gpio_smartbond_pin_configure,
383 .port_get_raw = gpio_smartbond_port_get_raw,
384 .port_set_masked_raw = gpio_smartbond_port_set_masked_raw,
385 .port_set_bits_raw = gpio_smartbond_port_set_bits_raw,
386 .port_clear_bits_raw = gpio_smartbond_port_clear_bits_raw,
387 .port_toggle_bits = gpio_smartbond_port_toggle_bits,
388 .pin_interrupt_configure = gpio_smartbond_pin_interrupt_configure,
389 .manage_callback = gpio_smartbond_manage_callback,
390 };
391
392 #define GPIO_SAVED_STATE(id) gpio_smartbond_saved_state_##id
393 #define GPIO_PM_DEVICE_CFG(fld, val) \
394 COND_CODE_1(CONFIG_PM_DEVICE, (fld = val,), ())
395 #define GPIO_PM_DEVICE_STATE(id, ngpios) \
396 COND_CODE_1(CONFIG_PM_DEVICE, (static uint32_t GPIO_SAVED_STATE(id)[1 + ngpios];), ())
397
398 #define GPIO_SMARTBOND_DEVICE(id) \
399 GPIO_PM_DEVICE_STATE(id, DT_INST_PROP(id, ngpios)) \
400 static const struct gpio_smartbond_config gpio_smartbond_config_##id = { \
401 .common = { \
402 .port_pin_mask = \
403 GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \
404 }, \
405 .data_regs = (volatile struct gpio_smartbond_data_regs *) \
406 DT_INST_REG_ADDR_BY_NAME(id, data), \
407 .mode_regs = (volatile uint32_t *)DT_INST_REG_ADDR_BY_NAME(id, mode), \
408 .latch_regs = (volatile struct gpio_smartbond_latch_regs *) \
409 DT_INST_REG_ADDR_BY_NAME(id, latch), \
410 .wkup_regs = (volatile struct gpio_smartbond_wkup_regs *) \
411 DT_INST_REG_ADDR_BY_NAME(id, wkup), \
412 .wkup_trig_select = id, \
413 GPIO_PM_DEVICE_CFG(.ngpios, DT_INST_PROP(id, ngpios)) \
414 }; \
415 \
416 static struct gpio_smartbond_data gpio_smartbond_data_##id = { \
417 GPIO_PM_DEVICE_CFG(.gpio_saved_state, GPIO_SAVED_STATE(id)) \
418 }; \
419 \
420 static int gpio_smartbond_init_##id(const struct device *dev) \
421 { \
422 da1469x_pd_acquire(MCU_PD_DOMAIN_COM); \
423 gpio_smartbond_wkup_init(); \
424 IRQ_CONNECT(DT_INST_IRQN(id), \
425 DT_INST_IRQ(id, priority), \
426 gpio_smartbond_isr, \
427 DEVICE_DT_INST_GET(id), 0); \
428 irq_enable(DT_INST_IRQN(id)); \
429 return 0; \
430 } \
431 \
432 PM_DEVICE_DEFINE(id, gpio_smartbond_pm_action); \
433 DEVICE_DT_INST_DEFINE(id, gpio_smartbond_init_##id, \
434 PM_DEVICE_GET(id), \
435 &gpio_smartbond_data_##id, \
436 &gpio_smartbond_config_##id, \
437 PRE_KERNEL_1, \
438 CONFIG_GPIO_INIT_PRIORITY, \
439 &gpio_smartbond_drv_api_funcs);
440
441 DT_INST_FOREACH_STATUS_OKAY(GPIO_SMARTBOND_DEVICE)
442
