1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2023 Google Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <string.h>
9
10 #include <zephyr/device.h>
11 #include <zephyr/drivers/flash.h>
12 #include <zephyr/init.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/sys/barrier.h>
16
17 #include <soc.h>
18
19 #include "flash_stm32.h"
20
21 LOG_MODULE_REGISTER(flash_stm32f4x, CONFIG_FLASH_LOG_LEVEL);
22
23 #if FLASH_STM32_WRITE_BLOCK_SIZE == 8
24 typedef uint64_t flash_prg_t;
25 #define FLASH_PROGRAM_SIZE FLASH_PSIZE_DOUBLE_WORD
26 #elif FLASH_STM32_WRITE_BLOCK_SIZE == 4
27 typedef uint32_t flash_prg_t;
28 #define FLASH_PROGRAM_SIZE FLASH_PSIZE_WORD
29 #elif FLASH_STM32_WRITE_BLOCK_SIZE == 2
30 typedef uint16_t flash_prg_t;
31 #define FLASH_PROGRAM_SIZE FLASH_PSIZE_HALF_WORD
32 #elif FLASH_STM32_WRITE_BLOCK_SIZE == 1
33 typedef uint8_t flash_prg_t;
34 #define FLASH_PROGRAM_SIZE FLASH_PSIZE_BYTE
35 #else
36 #error Write block size must be a power of 2, from 1 to 8
37 #endif
38
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)39 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
40 uint32_t len,
41 bool write)
42 {
43 ARG_UNUSED(write);
44
45 #if (FLASH_SECTOR_TOTAL == 12) && defined(FLASH_OPTCR_DB1M)
46 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
47 /*
48 * RM0090, table 7.1: STM32F42xxx, STM32F43xxx
49 */
50 if (regs->OPTCR & FLASH_OPTCR_DB1M) {
51 /* Device configured in Dual Bank, but not supported for now */
52 return false;
53 }
54 #endif
55
56 return flash_stm32_range_exists(dev, offset, len);
57 }
58
flush_cache(FLASH_TypeDef * regs)59 static inline void flush_cache(FLASH_TypeDef *regs)
60 {
61 if (regs->ACR & FLASH_ACR_DCEN) {
62 regs->ACR &= ~FLASH_ACR_DCEN;
63 /* Datasheet: DCRST: Data cache reset
64 * This bit can be written only when the data cache is disabled
65 */
66 regs->ACR |= FLASH_ACR_DCRST;
67 regs->ACR &= ~FLASH_ACR_DCRST;
68 regs->ACR |= FLASH_ACR_DCEN;
69 }
70
71 if (regs->ACR & FLASH_ACR_ICEN) {
72 regs->ACR &= ~FLASH_ACR_ICEN;
73 /* Datasheet: ICRST: Instruction cache reset :
74 * This bit can be written only when the instruction cache
75 * is disabled
76 */
77 regs->ACR |= FLASH_ACR_ICRST;
78 regs->ACR &= ~FLASH_ACR_ICRST;
79 regs->ACR |= FLASH_ACR_ICEN;
80 }
81 }
82
write_value(const struct device * dev,off_t offset,flash_prg_t val)83 static int write_value(const struct device *dev, off_t offset, flash_prg_t val)
84 {
85 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
86 #if defined(FLASH_OPTCR_DB1M)
87 bool dcache_enabled = false;
88 #endif /* FLASH_OPTCR_DB*/
89 uint32_t tmp;
90 int rc;
91
92 /* if the control register is locked, do not fail silently */
93 if (regs->CR & FLASH_CR_LOCK) {
94 return -EIO;
95 }
96
97 rc = flash_stm32_wait_flash_idle(dev);
98 if (rc < 0) {
99 return rc;
100 }
101
102 #if defined(FLASH_OPTCR_DB1M)
103 /*
104 * Disable the data cache to avoid the silicon errata ES0206 Rev 16 2.2.12:
105 * "Data cache might be corrupted during Flash memory read-while-write operation"
106 */
107 if (regs->ACR & FLASH_ACR_DCEN) {
108 dcache_enabled = true;
109 regs->ACR &= (~FLASH_ACR_DCEN);
110 }
111 #endif /* FLASH_OPTCR_DB1M */
112
113 regs->CR &= CR_PSIZE_MASK;
114 regs->CR |= FLASH_PROGRAM_SIZE;
115 regs->CR |= FLASH_CR_PG;
116
117 /* flush the register write */
118 tmp = regs->CR;
119
120 *((flash_prg_t *)(offset + FLASH_STM32_BASE_ADDRESS)) = val;
121
122 rc = flash_stm32_wait_flash_idle(dev);
123 regs->CR &= (~FLASH_CR_PG);
124
125 #if defined(FLASH_OPTCR_DB1M)
126 /* Reset/enable the data cache if previously enabled */
127 if (dcache_enabled) {
128 regs->ACR |= FLASH_ACR_DCRST;
129 regs->ACR &= (~FLASH_ACR_DCRST);
130 regs->ACR |= FLASH_ACR_DCEN;
131 }
132 #endif /* FLASH_OPTCR_DB1M */
133
134 return rc;
135 }
136
erase_sector(const struct device * dev,uint32_t sector)137 static int erase_sector(const struct device *dev, uint32_t sector)
138 {
139 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
140 uint32_t tmp;
141 int rc;
142
143 /* if the control register is locked, do not fail silently */
144 if (regs->CR & FLASH_CR_LOCK) {
145 return -EIO;
146 }
147
148 rc = flash_stm32_wait_flash_idle(dev);
149 if (rc < 0) {
150 return rc;
151 }
152
153 /*
154 * If an erase operation in Flash memory also concerns data
155 * in the instruction cache, the user has to ensure that these data
156 * are rewritten before they are accessed during code execution.
157 */
158 flush_cache(regs);
159
160 #if FLASH_SECTOR_TOTAL == 24
161 /*
162 * RM0090, §3.9.8: STM32F42xxx, STM32F43xxx
163 * RM0386, §3.7.5: STM32F469xx, STM32F479xx
164 */
165 if (sector >= 12) {
166 /* From sector 12, SNB is offset by 0b10000 */
167 sector += 4U;
168 }
169 #endif
170
171 regs->CR &= CR_PSIZE_MASK;
172 regs->CR |= FLASH_PROGRAM_SIZE;
173
174 regs->CR &= ~FLASH_CR_SNB;
175 regs->CR |= FLASH_CR_SER | (sector << 3);
176 regs->CR |= FLASH_CR_STRT;
177
178 /* flush the register write */
179 tmp = regs->CR;
180
181 rc = flash_stm32_wait_flash_idle(dev);
182 regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
183
184 return rc;
185 }
186
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)187 int flash_stm32_block_erase_loop(const struct device *dev,
188 unsigned int offset,
189 unsigned int len)
190 {
191 struct flash_pages_info info;
192 uint32_t start_sector, end_sector;
193 uint32_t i;
194 int rc = 0;
195
196 rc = flash_get_page_info_by_offs(dev, offset, &info);
197 if (rc) {
198 return rc;
199 }
200 start_sector = info.index;
201 rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info);
202 if (rc) {
203 return rc;
204 }
205 end_sector = info.index;
206
207 for (i = start_sector; i <= end_sector; i++) {
208 rc = erase_sector(dev, i);
209 if (rc < 0) {
210 break;
211 }
212 }
213
214 return rc;
215 }
216
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)217 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
218 const void *data, unsigned int len)
219 {
220 int i, rc = 0;
221 flash_prg_t value;
222
223 for (i = 0; i < len / sizeof(flash_prg_t); i++) {
224 value = UNALIGNED_GET((flash_prg_t *)data + i);
225 rc = write_value(dev, offset + i * sizeof(flash_prg_t), value);
226 if (rc < 0) {
227 return rc;
228 }
229 }
230
231 return rc;
232 }
233
write_optb(const struct device * dev,uint32_t mask,uint32_t value)234 static __unused int write_optb(const struct device *dev, uint32_t mask,
235 uint32_t value)
236 {
237 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
238 int rc;
239
240 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
241 return -EIO;
242 }
243
244 if ((regs->OPTCR & mask) == value) {
245 return 0;
246 }
247
248 rc = flash_stm32_wait_flash_idle(dev);
249 if (rc < 0) {
250 return rc;
251 }
252
253 regs->OPTCR = (regs->OPTCR & ~mask) | value;
254 regs->OPTCR |= FLASH_OPTCR_OPTSTRT;
255
256 /* Make sure previous write is completed. */
257 barrier_dsync_fence_full();
258
259 rc = flash_stm32_wait_flash_idle(dev);
260 if (rc < 0) {
261 return rc;
262 }
263
264 return 0;
265 }
266
267 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
flash_stm32_update_wp_sectors(const struct device * dev,uint32_t changed_sectors,uint32_t protected_sectors)268 int flash_stm32_update_wp_sectors(const struct device *dev,
269 uint32_t changed_sectors,
270 uint32_t protected_sectors)
271 {
272 changed_sectors <<= FLASH_OPTCR_nWRP_Pos;
273 protected_sectors <<= FLASH_OPTCR_nWRP_Pos;
274
275 if ((changed_sectors & FLASH_OPTCR_nWRP_Msk) != changed_sectors) {
276 return -EINVAL;
277 }
278
279 /* Sector is protected when bit == 0. Flip protected_sectors bits */
280 protected_sectors = ~protected_sectors & changed_sectors;
281
282 return write_optb(dev, changed_sectors, protected_sectors);
283 }
284
flash_stm32_get_wp_sectors(const struct device * dev,uint32_t * protected_sectors)285 int flash_stm32_get_wp_sectors(const struct device *dev,
286 uint32_t *protected_sectors)
287 {
288 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
289
290 *protected_sectors =
291 (~regs->OPTCR & FLASH_OPTCR_nWRP_Msk) >> FLASH_OPTCR_nWRP_Pos;
292
293 return 0;
294 }
295 #endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
296
297 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
flash_stm32_update_rdp(const struct device * dev,bool enable,bool permanent)298 int flash_stm32_update_rdp(const struct device *dev, bool enable,
299 bool permanent)
300 {
301 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
302 uint8_t current_level, target_level;
303
304 current_level =
305 (regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos;
306 target_level = current_level;
307
308 /*
309 * 0xAA = RDP level 0 (no protection)
310 * 0xCC = RDP level 2 (permanent protection)
311 * others = RDP level 1 (protection active)
312 */
313 switch (current_level) {
314 case FLASH_STM32_RDP2:
315 if (!enable || !permanent) {
316 LOG_ERR("RDP level 2 is permanent and can't be changed!");
317 return -ENOTSUP;
318 }
319 break;
320 case FLASH_STM32_RDP0:
321 if (enable) {
322 target_level = FLASH_STM32_RDP1;
323 if (permanent) {
324 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW)
325 target_level = FLASH_STM32_RDP2;
326 #else
327 LOG_ERR("Permanent readout protection (RDP "
328 "level 0 -> 2) not allowed");
329 return -ENOTSUP;
330 #endif
331 }
332 }
333 break;
334 default: /* FLASH_STM32_RDP1 */
335 if (enable && permanent) {
336 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW)
337 target_level = FLASH_STM32_RDP2;
338 #else
339 LOG_ERR("Permanent readout protection (RDP "
340 "level 1 -> 2) not allowed");
341 return -ENOTSUP;
342 #endif
343 }
344 if (!enable) {
345 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW)
346 target_level = FLASH_STM32_RDP0;
347 #else
348 LOG_ERR("Disabling readout protection (RDP "
349 "level 1 -> 0) not allowed");
350 return -EACCES;
351 #endif
352 }
353 }
354
355 /* Update RDP level if needed */
356 if (current_level != target_level) {
357 LOG_INF("RDP changed from 0x%02x to 0x%02x", current_level,
358 target_level);
359
360 write_optb(dev, FLASH_OPTCR_RDP_Msk,
361 (uint32_t)target_level << FLASH_OPTCR_RDP_Pos);
362 }
363 return 0;
364 }
365
flash_stm32_get_rdp(const struct device * dev,bool * enabled,bool * permanent)366 int flash_stm32_get_rdp(const struct device *dev, bool *enabled,
367 bool *permanent)
368 {
369 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
370 uint8_t current_level;
371
372 current_level =
373 (regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos;
374
375 /*
376 * 0xAA = RDP level 0 (no protection)
377 * 0xCC = RDP level 2 (permanent protection)
378 * others = RDP level 1 (protection active)
379 */
380 switch (current_level) {
381 case FLASH_STM32_RDP2:
382 *enabled = true;
383 *permanent = true;
384 break;
385 case FLASH_STM32_RDP0:
386 *enabled = false;
387 *permanent = false;
388 break;
389 default: /* FLASH_STM32_RDP1 */
390 *enabled = true;
391 *permanent = false;
392 }
393 return 0;
394 }
395 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
396
397 /*
398 * Different SoC flash layouts are specified in across various
399 * reference manuals, but the flash layout for a given number of
400 * sectors is consistent across these manuals, with one "gotcha". The
401 * number of sectors is given by the HAL as FLASH_SECTOR_TOTAL.
402 *
403 * The only "gotcha" is that when there are 24 sectors, they are split
404 * across 2 "banks" of 12 sectors each, with another set of small
405 * sectors (16 KB) in the second bank occurring after the large ones
406 * (128 KB) in the first. We could consider supporting this as two
407 * devices to make the layout cleaner, but this will do for now.
408 */
409 #ifndef FLASH_SECTOR_TOTAL
410 #error "Unknown flash layout"
411 #else /* defined(FLASH_SECTOR_TOTAL) */
412 #if FLASH_SECTOR_TOTAL == 5
413 static const struct flash_pages_layout stm32f4_flash_layout[] = {
414 /* RM0401, table 5: STM32F410Tx, STM32F410Cx, STM32F410Rx */
415 {.pages_count = 4, .pages_size = KB(16)},
416 {.pages_count = 1, .pages_size = KB(64)},
417 };
418 #elif FLASH_SECTOR_TOTAL == 6
419 static const struct flash_pages_layout stm32f4_flash_layout[] = {
420 /* RM0368, table 5: STM32F401xC */
421 {.pages_count = 4, .pages_size = KB(16)},
422 {.pages_count = 1, .pages_size = KB(64)},
423 {.pages_count = 1, .pages_size = KB(128)},
424 };
425 #elif FLASH_SECTOR_TOTAL == 8
426 static const struct flash_pages_layout stm32f4_flash_layout[] = {
427 /*
428 * RM0368, table 5: STM32F401xE
429 * RM0383, table 4: STM32F411xE
430 * RM0390, table 4: STM32F446xx
431 */
432 {.pages_count = 4, .pages_size = KB(16)},
433 {.pages_count = 1, .pages_size = KB(64)},
434 {.pages_count = 3, .pages_size = KB(128)},
435 };
436 #elif FLASH_SECTOR_TOTAL == 12
437 static const struct flash_pages_layout stm32f4_flash_layout[] = {
438 /*
439 * RM0090, table 5: STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx
440 * RM0402, table 5: STM32F412Zx, STM32F412Vx, STM32F412Rx, STM32F412Cx
441 */
442 {.pages_count = 4, .pages_size = KB(16)},
443 {.pages_count = 1, .pages_size = KB(64)},
444 {.pages_count = 7, .pages_size = KB(128)},
445 };
446 #elif FLASH_SECTOR_TOTAL == 16
447 static const struct flash_pages_layout stm32f4_flash_layout[] = {
448 /* RM0430, table 5.: STM32F413xx, STM32F423xx */
449 {.pages_count = 4, .pages_size = KB(16)},
450 {.pages_count = 1, .pages_size = KB(64)},
451 {.pages_count = 11, .pages_size = KB(128)},
452 };
453 #elif FLASH_SECTOR_TOTAL == 24
454 static const struct flash_pages_layout stm32f4_flash_layout[] = {
455 /*
456 * RM0090, table 6: STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx
457 * RM0386, table 4: STM32F469xx, STM32F479xx
458 */
459 {.pages_count = 4, .pages_size = KB(16)},
460 {.pages_count = 1, .pages_size = KB(64)},
461 {.pages_count = 7, .pages_size = KB(128)},
462 {.pages_count = 4, .pages_size = KB(16)},
463 {.pages_count = 1, .pages_size = KB(64)},
464 {.pages_count = 7, .pages_size = KB(128)},
465 };
466 #else
467 #error "Unknown flash layout"
468 #endif /* FLASH_SECTOR_TOTAL == 5 */
469 #endif/* !defined(FLASH_SECTOR_TOTAL) */
470
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)471 void flash_stm32_page_layout(const struct device *dev,
472 const struct flash_pages_layout **layout,
473 size_t *layout_size)
474 {
475 ARG_UNUSED(dev);
476
477 *layout = stm32f4_flash_layout;
478 *layout_size = ARRAY_SIZE(stm32f4_flash_layout);
479 }
480
