1 /* 2 * Copyright (c) 2023 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ 8 #define ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ 9 10 #include <zephyr/device.h> 11 #include "jesd216.h" 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /* UMA operation flags */ 18 #define NPCX_UMA_ACCESS_WRITE BIT(0) 19 #define NPCX_UMA_ACCESS_READ BIT(1) 20 #define NPCX_UMA_ACCESS_ADDR BIT(2) 21 22 /* Valid value of Dn_NADDRB that sets the number of address bytes in a transaction */ 23 #define NPCX_DEV_NUM_ADDR_1BYTE 1 24 #define NPCX_DEV_NUM_ADDR_2BYTE 2 25 #define NPCX_DEV_NUM_ADDR_3BYTE 3 26 #define NPCX_DEV_NUM_ADDR_4BYTE 4 27 28 /* UMA operation configuration for a SPI device */ 29 struct npcx_uma_cfg { 30 uint8_t opcode; 31 uint8_t *tx_buf; 32 size_t tx_count; 33 uint8_t *rx_buf; 34 size_t rx_count; 35 union { 36 uint32_t u32; 37 uint8_t u8[4]; 38 } addr; 39 }; 40 41 /* QSPI bus configuration for a SPI device */ 42 struct npcx_qspi_cfg { 43 /* Type of Quad Enable bit in status register */ 44 enum jesd216_dw15_qer_type qer_type; 45 /* Pinctrl for QSPI bus */ 46 const struct pinctrl_dev_config *pcfg; 47 /* Enter four bytes address mode value */ 48 uint8_t enter_4ba; 49 /* SPI read access type of Direct Read Access mode */ 50 uint8_t rd_mode; 51 /* Configurations for the Quad-SPI peripherals */ 52 int flags; 53 }; 54 55 /** 56 * @brief Execute UMA transactions on qspi bus 57 * 58 * @param dev Pointer to the device structure for qspi bus controller instance. 59 * @param cfg Pointer to the configuration of UMA transactions. 60 * @param flags Flags to be used during transactions. 61 * @retval 0 on success, -EPERM if an UMA transaction is not permitted. 62 */ 63 int qspi_npcx_fiu_uma_transceive(const struct device *dev, struct npcx_uma_cfg *cfg, 64 uint32_t flags); 65 66 /** 67 * @brief Lock the mutex of npcx qspi bus controller and apply its configuration 68 * 69 * @param dev Pointer to the device structure for qspi bus controller instance. 70 * @param cfg Pointer to the configuration for the device on qspi bus. 71 * @param operation Qspi bus operation for the device. 72 */ 73 void qspi_npcx_fiu_mutex_lock_configure(const struct device *dev, 74 const struct npcx_qspi_cfg *cfg, 75 const uint32_t operation); 76 77 /** 78 * @brief Unlock the mutex of npcx qspi bus controller. 79 * 80 * @param dev Pointer to the device structure for qspi bus controller instance. 81 */ 82 void qspi_npcx_fiu_mutex_unlock(const struct device *dev); 83 84 #ifdef __cplusplus 85 } 86 #endif 87 88 #endif /* ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ */ 89
