1# Copyright (c) 2022 Intel Corporation.
2# SPDX-License-Identifier: Apache-2.0
3
4config FLASH_CAD_QSPI_NOR
5	bool "Cadence Quad SPI Flash driver"
6	default y
7	depends on DT_HAS_CDNS_QSPI_NOR_ENABLED
8	select FLASH_HAS_PAGE_LAYOUT
9	select FLASH_HAS_DRIVER_ENABLED
10	select FLASH_HAS_EXPLICIT_ERASE
11	help
12	  Enable Cadence QSPI-NOR support.
13
14if FLASH_CAD_QSPI_NOR
15
16config CAD_QSPI_MICRON_N25Q_SUPPORT
17	bool "Cadence Quad SPI Micron N25Q Support"
18	default y
19	help
20	  Enable Micron N25Q Support.
21
22config CAD_QSPI_NOR_SUBSECTOR_SIZE
23	hex "Cadence Quad SPI subsector size"
24	default 0x1000
25	help
26	  Set the Cadence Quad SPI subsector size.
27
28config QSPI_ADDR_BYTES
29	int "Access QSPI address memory size in bytes"
30	default 2
31	help
32	  Set the address memory size in bytes when
33	  accessing QSPI.
34
35config QSPI_BYTES_PER_DEV
36	int "Set QSPI to read / write how many bytes per device"
37	default 256
38	help
39	  Set the size for a QSPI to read / write per device.
40
41config QSPI_BYTES_PER_BLOCK
42	int "Set QSPI to read / write how many bytes per block"
43	default 16
44	help
45	  Set the size for a QSPI to read / write per block.
46
47endif # FLASH_CAD_QSPI_NOR
48