1 /* 2 * Xilinx Processor System Gigabit Ethernet controller (GEM) driver 3 * 4 * Driver private data declarations 5 * 6 * Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 #ifndef _ZEPHYR_DRIVERS_ETHERNET_ETH_XLNX_GEM_PRIV_H_ 11 #define _ZEPHYR_DRIVERS_ETHERNET_ETH_XLNX_GEM_PRIV_H_ 12 13 #define DT_DRV_COMPAT xlnx_gem 14 15 #include <zephyr/kernel.h> 16 #include <zephyr/types.h> 17 #include <zephyr/net/net_pkt.h> 18 #include <zephyr/irq.h> 19 20 #include "phy_xlnx_gem.h" 21 22 #define ETH_XLNX_BUFFER_ALIGNMENT 4 /* RX/TX buffer alignment (in bytes) */ 23 24 /* Buffer descriptor (BD) related defines */ 25 26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */ 27 28 /* 29 * Receive Buffer Descriptor address word: 30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0] 31 * [01] Wrap bit, last BD in RX BD ring 32 * [00] BD used bit 33 */ 34 #define ETH_XLNX_GEM_RXBD_WRAP_BIT 0x00000002 35 #define ETH_XLNX_GEM_RXBD_USED_BIT 0x00000001 36 #define ETH_XLNX_GEM_RXBD_BUFFER_ADDR_MASK 0xFFFFFFFC 37 38 /* 39 * Receive Buffer Descriptor control word: 40 * [31] Broadcast detected 41 * [30] Multicast hash match detected 42 * [29] Unicast hash match detected 43 * [27] Specific address match detected 44 * [26 .. 25] Bits indicating which specific address register was matched 45 * [24] this bit has different semantics depending on whether RX checksum 46 * offloading is enabled or not 47 * [23 .. 22] These bits have different semantics depending on whether RX check- 48 * sum offloading is enabled or not 49 * [21] VLAN tag (type ID 0x8100) detected 50 * [20] Priority tag: VLAN tag (type ID 0x8100) and null VLAN identifier 51 * detected 52 * [19 .. 17] VLAN priority 53 * [16] Canonical format indicator bit 54 * [15] End-of-frame bit 55 * [14] Start-of-frame bit 56 * [13] FCS status bit for FCS ignore mode 57 * [12 .. 00] Data length of received frame 58 */ 59 #define ETH_XLNX_GEM_RXBD_BCAST_BIT 0x80000000 60 #define ETH_XLNX_GEM_RXBD_MCAST_HASH_MATCH_BIT 0x40000000 61 #define ETH_XLNX_GEM_RXBD_UCAST_HASH_MATCH_BIT 0x20000000 62 #define ETH_XLNX_GEM_RXBD_SPEC_ADDR_MATCH_BIT 0x08000000 63 #define ETH_XLNX_GEM_RXBD_SPEC_ADDR_MASK 0x00000003 64 #define ETH_XLNX_GEM_RXBD_SPEC_ADDR_SHIFT 25 65 #define ETH_XLNX_GEM_RXBD_BIT24 0x01000000 66 #define ETH_XLNX_GEM_RXBD_BITS23_22_MASK 0x00000003 67 #define ETH_XLNX_GEM_RXBD_BITS23_22_SHIFT 22 68 #define ETH_XLNX_GEM_RXBD_VLAN_TAG_DETECTED_BIT 0x00200000 69 #define ETH_XLNX_GEM_RXBD_PRIO_TAG_DETECTED_BIT 0x00100000 70 #define ETH_XLNX_GEM_RXBD_VLAN_PRIORITY_MASK 0x00000007 71 #define ETH_XLNX_GEM_RXBD_VLAN_PRIORITY_SHIFT 17 72 #define ETH_XLNX_GEM_RXBD_CFI_BIT 0x00010000 73 #define ETH_XLNX_GEM_RXBD_END_OF_FRAME_BIT 0x00008000 74 #define ETH_XLNX_GEM_RXBD_START_OF_FRAME_BIT 0x00004000 75 #define ETH_XLNX_GEM_RXBD_FCS_STATUS_BIT 0x00002000 76 #define ETH_XLNX_GEM_RXBD_FRAME_LENGTH_MASK 0x00001FFF 77 78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */ 79 80 /* 81 * Transmit Buffer Descriptor control word: 82 * [31] BD used marker 83 * [30] Wrap bit, last BD in TX BD ring 84 * [29] Retry limit exceeded 85 * [27] TX frame corruption due to AHB/AXI error, HRESP errors or buffers 86 * exhausted mid-frame 87 * [26] Late collision, TX error detected 88 * [22 .. 20] Transmit IP/TCP/UDP checksum generation offload error bits 89 * [16] No CRC appended by MAC 90 * [15] Last buffer bit, indicates end of current TX frame 91 * [13 .. 00] Data length in the BD's associated buffer 92 */ 93 #define ETH_XLNX_GEM_TXBD_USED_BIT 0x80000000 94 #define ETH_XLNX_GEM_TXBD_WRAP_BIT 0x40000000 95 #define ETH_XLNX_GEM_TXBD_RETRY_BIT 0x20000000 96 #define ETH_XLNX_GEM_TXBD_TX_FRAME_CORRUPT_BIT 0x08000000 97 #define ETH_XLNX_GEM_TXBD_LATE_COLLISION_BIT 0x04000000 98 #define ETH_XLNX_GEM_TXBD_CKSUM_OFFLOAD_ERROR_MASK 0x00000007 99 #define ETH_XLNX_GEM_TXBD_CKSUM_OFFLOAD_ERROR_SHIFT 20 100 #define ETH_XLNX_GEM_TXBD_NO_CRC_BIT 0x00010000 101 #define ETH_XLNX_GEM_TXBD_LAST_BIT 0x00008000 102 #define ETH_XLNX_GEM_TXBD_LEN_MASK 0x00003FFF 103 #define ETH_XLNX_GEM_TXBD_ERR_MASK 0x3C000000 104 105 #define ETH_XLNX_GEM_CKSUM_NO_ERROR 0x00000000 106 #define ETH_XLNX_GEM_CKSUM_VLAN_HDR_ERROR 0x00000001 107 #define ETH_XLNX_GEM_CKSUM_SNAP_HDR_ERROR 0x00000002 108 #define ETH_XLNX_GEM_CKSUM_IP_TYPE_OR_LEN_ERROR 0x00000003 109 #define ETH_XLNX_GEM_CKSUM_NOT_VLAN_SNAP_IP_ERROR 0x00000004 110 #define ETH_XLNX_GEM_CKSUM_UNSUPP_PKT_FRAG_ERROR 0x00000005 111 #define ETH_XLNX_GEM_CKSUM_NOT_TCP_OR_UDP_ERROR 0x00000006 112 #define ETH_XLNX_GEM_CKSUM_PREMATURE_END_ERROR 0x00000007 113 114 #if defined(CONFIG_SOC_FAMILY_XILINX_ZYNQ7000) 115 /* 116 * Zynq-7000 TX clock configuration: 117 * 118 * GEMx_CLK_CTRL (SLCR) registers: 119 * [25 .. 20] Reference clock divisor 1 120 * [13 .. 08] Reference clock divisor 0 121 * [00] Clock active bit 122 */ 123 #define ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK 0x0000003F 124 #define ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR1_SHIFT 20 125 #define ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR0_SHIFT 8 126 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_CLKACT_BIT 0x02000000 127 #elif defined(CONFIG_SOC_XILINX_ZYNQMP) 128 /* 129 * UltraScale TX clock configuration: comp. 130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html 131 * 132 * CRL_WPROT (CRL_APB) register: 133 * [00] CRL APB register space write protection bit 134 * 135 * GEMx_REF_CTRL (CRL_APB) registers: 136 * [30] RX channel clock active bit 137 * [29] Clock active bit 138 * [21 .. 16] Reference clock divisor 1 139 * [13 .. 08] Reference clock divisor 0 140 */ 141 #define ETH_XLNX_CRL_APB_WPROT_REGISTER_ADDRESS 0xFF5E001C 142 #define ETH_XLNX_CRL_APB_WPROT_BIT 0x00000001 143 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR_MASK 0x0000003F 144 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR1_SHIFT 16 145 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR0_SHIFT 8 146 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_RX_CLKACT_BIT 0x04000000 147 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_CLKACT_BIT 0x02000000 148 #endif /* CONFIG_SOC_FAMILY_XILINX_ZYNQ7000 || CONFIG_SOC_XILINX_ZYNQMP */ 149 150 /* 151 * Register offsets within the respective GEM's address space: 152 * NWCTRL = gem.net_ctrl Network Control register 153 * NWCFG = gem.net_cfg Network Configuration register 154 * NWSR = gem.net_status Network Status register 155 * DMACR = gem.dma_cfg DMA Control register 156 * TXSR = gem.tx_status TX Status register 157 * RXQBASE = gem.rx_qbar RXQ base address register 158 * TXQBASE = gem.tx_qbar TXQ base address register 159 * RXSR = gem.rx_status RX Status register 160 * ISR = gem.intr_status Interrupt status register 161 * IER = gem.intr_en Interrupt enable register 162 * IDR = gem.intr_dis Interrupt disable register 163 * IMR = gem.intr_mask Interrupt mask register 164 * PHYMNTNC = gem.phy_maint PHY maintenance register 165 * LADDR1L = gem.spec_addr1_bot Specific address 1 bottom register 166 * LADDR1H = gem.spec_addr1_top Specific address 1 top register 167 * LADDR2L = gem.spec_addr2_bot Specific address 2 bottom register 168 * LADDR2H = gem.spec_addr2_top Specific address 2 top register 169 * LADDR3L = gem.spec_addr3_bot Specific address 3 bottom register 170 * LADDR3H = gem.spec_addr3_top Specific address 3 top register 171 * LADDR4L = gem.spec_addr4_bot Specific address 4 bottom register 172 * LADDR4H = gem.spec_addr4_top Specific address 4 top register 173 */ 174 #define ETH_XLNX_GEM_NWCTRL_OFFSET 0x00000000 175 #define ETH_XLNX_GEM_NWCFG_OFFSET 0x00000004 176 #define ETH_XLNX_GEM_NWSR_OFFSET 0x00000008 177 #define ETH_XLNX_GEM_DMACR_OFFSET 0x00000010 178 #define ETH_XLNX_GEM_TXSR_OFFSET 0x00000014 179 #define ETH_XLNX_GEM_RXQBASE_OFFSET 0x00000018 180 #define ETH_XLNX_GEM_TXQBASE_OFFSET 0x0000001C 181 #define ETH_XLNX_GEM_RXSR_OFFSET 0x00000020 182 #define ETH_XLNX_GEM_ISR_OFFSET 0x00000024 183 #define ETH_XLNX_GEM_IER_OFFSET 0x00000028 184 #define ETH_XLNX_GEM_IDR_OFFSET 0x0000002C 185 #define ETH_XLNX_GEM_IMR_OFFSET 0x00000030 186 #define ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET 0x00000034 187 #define ETH_XLNX_GEM_LADDR1L_OFFSET 0x00000088 188 #define ETH_XLNX_GEM_LADDR1H_OFFSET 0x0000008C 189 #define ETH_XLNX_GEM_LADDR2L_OFFSET 0x00000090 190 #define ETH_XLNX_GEM_LADDR2H_OFFSET 0x00000094 191 #define ETH_XLNX_GEM_LADDR3L_OFFSET 0x00000098 192 #define ETH_XLNX_GEM_LADDR3H_OFFSET 0x0000009C 193 #define ETH_XLNX_GEM_LADDR4L_OFFSET 0x000000A0 194 #define ETH_XLNX_GEM_LADDR4H_OFFSET 0x000000A4 195 196 /* 197 * Masks for clearing registers during initialization: 198 * gem.net_ctrl [clear_stat_regs] 199 * gem.tx_status [7..0] 200 * gem.rx_status [3..0] 201 * gem.intr_dis [26..0] 202 */ 203 #define ETH_XLNX_GEM_STATCLR_MASK 0x00000020 204 #define ETH_XLNX_GEM_TXSRCLR_MASK 0x000000FF 205 #define ETH_XLNX_GEM_RXSRCLR_MASK 0x0000000F 206 #define ETH_XLNX_GEM_IDRCLR_MASK 0x07FFFFFF 207 208 /* (Shift) masks for individual registers' bits / bitfields */ 209 210 /* 211 * gem.net_ctrl: 212 * [15] Store 1588 receive timestamp in CRC field 213 * [12] Transmit zero quantum pause frame 214 * [11] Transmit pause frame 215 * [10] Halt transmission after current frame 216 * [09] Start transmission (tx_go) 217 * [07] Enable writing to statistics counters 218 * [06] Increment statistics registers - for testing purposes only 219 * [05] Clear statistics registers 220 * [04] Enable MDIO port 221 * [03] Enable transmit 222 * [02] Enable receive 223 * [01] Local loopback mode 224 */ 225 #define ETH_XLNX_GEM_NWCTRL_RXTSTAMP_BIT 0x00008000 226 #define ETH_XLNX_GEM_NWCTRL_ZEROPAUSETX_BIT 0x00001000 227 #define ETH_XLNX_GEM_NWCTRL_PAUSETX_BIT 0x00000800 228 #define ETH_XLNX_GEM_NWCTRL_HALTTX_BIT 0x00000400 229 #define ETH_XLNX_GEM_NWCTRL_STARTTX_BIT 0x00000200 230 #define ETH_XLNX_GEM_NWCTRL_STATWEN_BIT 0x00000080 231 #define ETH_XLNX_GEM_NWCTRL_STATINC_BIT 0x00000040 232 #define ETH_XLNX_GEM_NWCTRL_STATCLR_BIT 0x00000020 233 #define ETH_XLNX_GEM_NWCTRL_MDEN_BIT 0x00000010 234 #define ETH_XLNX_GEM_NWCTRL_TXEN_BIT 0x00000008 235 #define ETH_XLNX_GEM_NWCTRL_RXEN_BIT 0x00000004 236 #define ETH_XLNX_GEM_NWCTRL_LOOPEN_BIT 0x00000002 237 238 /* 239 * gem.net_cfg: 240 * [30] Ignore IPG RX Error 241 * [29] Disable rejection of non-standard preamble 242 * [28] Enable IPG stretch 243 * [27] Enable SGMII mode 244 * [26] Disable rejection of frames with FCS errors 245 * [25] Enable frames to be received in HDX mode while transmitting 246 * [24] Enable RX checksum offload to hardware 247 * [23] Do not copy pause frames to memory 248 * [22 .. 21] Data bus width 249 * [20 .. 18] MDC clock division setting 250 * [17] Discard FCS from received frames 251 * [16] RX length field error frame discard enable 252 * [15 .. 14] Receive buffer offset, # of bytes 253 * [13] Enable pause TX upon 802.3 pause frame reception 254 * [12] Retry test - for testing purposes only 255 * [11] Use TBI instead of the GMII/MII interface 256 * [10] Gigabit mode enable 257 * [09] External address match enable 258 * [08] Enable 1536 byte frames reception 259 * [07] Receive unicast hash frames enable 260 * [06] Receive multicast hash frames enable 261 * [05] Disable broadcast frame reception 262 * [04] Copy all frames = promiscuous mode 263 * [02] Discard non-VLAN frames enable 264 * [01] Full duplex enable 265 * [00] Speed selection: 1 = 100Mbit/s, 0 = 10 Mbit/s, GBE mode is 266 * set separately in bit [10] 267 */ 268 #define ETH_XLNX_GEM_NWCFG_IGNIPGRXERR_BIT 0x40000000 269 #define ETH_XLNX_GEM_NWCFG_BADPREAMBEN_BIT 0x20000000 270 #define ETH_XLNX_GEM_NWCFG_IPG_STRETCH_BIT 0x10000000 271 #define ETH_XLNX_GEM_NWCFG_SGMIIEN_BIT 0x08000000 272 #define ETH_XLNX_GEM_NWCFG_FCSIGNORE_BIT 0x04000000 273 #define ETH_XLNX_GEM_NWCFG_HDRXEN_BIT 0x02000000 274 #define ETH_XLNX_GEM_NWCFG_RXCHKSUMEN_BIT 0x01000000 275 #define ETH_XLNX_GEM_NWCFG_PAUSECOPYDI_BIT 0x00800000 276 #define ETH_XLNX_GEM_NWCFG_DBUSW_MASK 0x3 277 #define ETH_XLNX_GEM_NWCFG_DBUSW_SHIFT 21 278 #define ETH_XLNX_GEM_NWCFG_MDC_MASK 0x7 279 #define ETH_XLNX_GEM_NWCFG_MDC_SHIFT 18 280 #define ETH_XLNX_GEM_NWCFG_MDCCLKDIV_MASK 0x001C0000 281 #define ETH_XLNX_GEM_NWCFG_FCSREM_BIT 0x00020000 282 #define ETH_XLNX_GEM_NWCFG_LENGTHERRDSCRD_BIT 0x00010000 283 #define ETH_XLNX_GEM_NWCFG_RXOFFS_MASK 0x00000003 284 #define ETH_XLNX_GEM_NWCFG_RXOFFS_SHIFT 14 285 #define ETH_XLNX_GEM_NWCFG_PAUSEEN_BIT 0x00002000 286 #define ETH_XLNX_GEM_NWCFG_RETRYTESTEN_BIT 0x00001000 287 #define ETH_XLNX_GEM_NWCFG_TBIINSTEAD_BIT 0x00000800 288 #define ETH_XLNX_GEM_NWCFG_1000_BIT 0x00000400 289 #define ETH_XLNX_GEM_NWCFG_EXTADDRMATCHEN_BIT 0x00000200 290 #define ETH_XLNX_GEM_NWCFG_1536RXEN_BIT 0x00000100 291 #define ETH_XLNX_GEM_NWCFG_UCASTHASHEN_BIT 0x00000080 292 #define ETH_XLNX_GEM_NWCFG_MCASTHASHEN_BIT 0x00000040 293 #define ETH_XLNX_GEM_NWCFG_BCASTDIS_BIT 0x00000020 294 #define ETH_XLNX_GEM_NWCFG_COPYALLEN_BIT 0x00000010 295 #define ETH_XLNX_GEM_NWCFG_NVLANDISC_BIT 0x00000004 296 #define ETH_XLNX_GEM_NWCFG_FDEN_BIT 0x00000002 297 #define ETH_XLNX_GEM_NWCFG_100_BIT 0x00000001 298 299 /* 300 * gem.dma_cfg: 301 * [24] Discard packets when AHB resource is unavailable 302 * [23 .. 16] RX buffer size, n * 64 bytes 303 * [11] Enable/disable TCP|UDP/IP TX checksum offload 304 * [10] TX buffer half/full memory size 305 * [09 .. 08] Receiver packet buffer memory size select 306 * [07] Endianness configuration 307 * [06] Descriptor access endianness configuration 308 * [04 .. 00] AHB fixed burst length for DMA data operations 309 */ 310 #define ETH_XLNX_GEM_DMACR_DISCNOAHB_BIT 0x01000000 311 #define ETH_XLNX_GEM_DMACR_RX_BUF_MASK 0x000000FF 312 #define ETH_XLNX_GEM_DMACR_RX_BUF_SHIFT 16 313 #define ETH_XLNX_GEM_DMACR_TCP_CHKSUM_BIT 0x00000800 314 #define ETH_XLNX_GEM_DMACR_TX_SIZE_BIT 0x00000400 315 #define ETH_XLNX_GEM_DMACR_RX_SIZE_MASK 0x00000300 316 #define ETH_XLNX_GEM_DMACR_RX_SIZE_SHIFT 8 317 #define ETH_XLNX_GEM_DMACR_ENDIAN_BIT 0x00000080 318 #define ETH_XLNX_GEM_DMACR_DESCR_ENDIAN_BIT 0x00000040 319 #define ETH_XLNX_GEM_DMACR_AHB_BURST_LENGTH_MASK 0x0000001F 320 321 /* 322 * gem.intr_* interrupt status/enable/disable bits: 323 * [25] PTP pdelay_resp frame transmitted 324 * [24] PTP pdelay_req frame transmitted 325 * [23] PTP pdelay_resp frame received 326 * [22] PTP delay_req frame received 327 * [21] PTP sync frame transmitted 328 * [20] PTP delay_req frame transmitted 329 * [19] PTP sync frame received 330 * [18] PTP delay_req frame received 331 * [17] PCS link partner page mask 332 * [16] Auto-negotiation completed 333 * [15] External interrupt 334 * [14] Pause frame transmitted 335 * [13] Pause time has reached zero 336 * [12] Pause frame received with non-zero pause quantum 337 * [11] hresp not OK 338 * [10] Receive overrun 339 * [09] Link change 340 * [07] Transmit complete 341 * [06] Transmit frame corruption due to AHB/AXI error 342 * [05] Retry limit exceeded or late collision 343 * [04] Transmit buffer underrun 344 * [03] Set 'used' bit in TX BD encountered 345 * [02] Set 'used' bit in RX BD encountered 346 * [01] Frame received 347 * [00] PHY management done 348 */ 349 #define ETH_XLNX_GEM_IXR_PTPPSTX_BIT 0x02000000 350 #define ETH_XLNX_GEM_IXR_PTPPDRTX_BIT 0x01000000 351 #define ETH_XLNX_GEM_IXR_PTPSTX_BIT 0x00800000 352 #define ETH_XLNX_GEM_IXR_PTPDRTX_BIT 0x00400000 353 #define ETH_XLNX_GEM_IXR_PTPPSRX_BIT 0x00200000 354 #define ETH_XLNX_GEM_IXR_PTPPDRRX_BIT 0x00100000 355 #define ETH_XLNX_GEM_IXR_PTPSRX_BIT 0x00080000 356 #define ETH_XLNX_GEM_IXR_PTPDRRX_BIT 0x00040000 357 #define ETH_XLNX_GEM_IXR_PARTNER_PGRX_BIT 0x00020000 358 #define ETH_XLNX_GEM_IXR_AUTONEG_COMPLETE_BIT 0x00010000 359 #define ETH_XLNX_GEM_IXR_EXTERNAL_INT_BIT 0x00008000 360 #define ETH_XLNX_GEM_IXR_PAUSE_TX_BIT 0x00004000 361 #define ETH_XLNX_GEM_IXR_PAUSE_ZERO_BIT 0x00002000 362 #define ETH_XLNX_GEM_IXR_PAUSE_NONZERO_BIT 0x00001000 363 #define ETH_XLNX_GEM_IXR_HRESP_NOT_OK_BIT 0x00000800 364 #define ETH_XLNX_GEM_IXR_RX_OVERRUN_BIT 0x00000400 365 #define ETH_XLNX_GEM_IXR_LINK_CHANGE 0x00000200 366 #define ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT 0x00000080 367 #define ETH_XLNX_GEM_IXR_TX_CORRUPT_BIT 0x00000040 368 #define ETH_XLNX_GEM_IXR_RETRY_LIMIT_OR_LATE_COLL_BIT 0x00000020 369 #define ETH_XLNX_GEM_IXR_TX_UNDERRUN_BIT 0x00000010 370 #define ETH_XLNX_GEM_IXR_TX_USED_BIT 0x00000008 371 #define ETH_XLNX_GEM_IXR_RX_USED_BIT 0x00000004 372 #define ETH_XLNX_GEM_IXR_FRAME_RX_BIT 0x00000002 373 #define ETH_XLNX_GEM_IXR_PHY_MGMNT_BIT 0x00000001 374 #define ETH_XLNX_GEM_IXR_ALL_MASK 0x03FC7FFE 375 #define ETH_XLNX_GEM_IXR_ERRORS_MASK 0x00000C60 376 377 /* Bits / bit masks relating to the GEM's MDIO interface */ 378 379 /* 380 * gem.net_status: 381 * [02] PHY management idle bit 382 * [01] MDIO input status 383 */ 384 #define ETH_XLNX_GEM_MDIO_IDLE_BIT 0x00000004 385 #define ETH_XLNX_GEM_MDIO_IN_STATUS_BIT 0x00000002 386 387 /* 388 * gem.phy_maint: 389 * [31 .. 30] constant values 390 * [17 .. 16] constant values 391 * [29] Read operation control bit 392 * [28] Write operation control bit 393 * [27 .. 23] PHY address 394 * [22 .. 18] Register address 395 * [15 .. 00] 16-bit data word 396 */ 397 #define ETH_XLNX_GEM_PHY_MAINT_CONST_BITS 0x40020000 398 #define ETH_XLNX_GEM_PHY_MAINT_READ_OP_BIT 0x20000000 399 #define ETH_XLNX_GEM_PHY_MAINT_WRITE_OP_BIT 0x10000000 400 #define ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK 0x0000001F 401 #define ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_SHIFT 23 402 #define ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_MASK 0x0000001F 403 #define ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_SHIFT 18 404 #define ETH_XLNX_GEM_PHY_MAINT_DATA_MASK 0x0000FFFF 405 406 /* Device initialization macro */ 407 #define ETH_XLNX_GEM_NET_DEV_INIT(port) \ 408 ETH_NET_DEVICE_DT_INST_DEFINE(port,\ 409 eth_xlnx_gem_dev_init,\ 410 NULL,\ 411 ð_xlnx_gem##port##_dev_data,\ 412 ð_xlnx_gem##port##_dev_cfg,\ 413 CONFIG_ETH_INIT_PRIORITY,\ 414 ð_xlnx_gem_apis,\ 415 NET_ETH_MTU); 416 417 /* Device configuration data declaration macro */ 418 #define ETH_XLNX_GEM_DEV_CONFIG(port) \ 419 static const struct eth_xlnx_gem_dev_cfg eth_xlnx_gem##port##_dev_cfg = {\ 420 .base_addr = DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0),\ 421 .config_func = eth_xlnx_gem##port##_irq_config,\ 422 .pll_clock_frequency = DT_INST_PROP(port, clock_frequency),\ 423 .clk_ctrl_reg_address = DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 1),\ 424 .mdc_divider = (enum eth_xlnx_mdc_clock_divider)\ 425 (DT_INST_PROP(port, mdc_divider)),\ 426 .max_link_speed = (enum eth_xlnx_link_speed)\ 427 (DT_INST_PROP(port, link_speed)),\ 428 .init_phy = DT_INST_PROP(port, init_mdio_phy),\ 429 .phy_mdio_addr_fix = DT_INST_PROP(port, mdio_phy_address),\ 430 .phy_advertise_lower = DT_INST_PROP(port, advertise_lower_link_speeds),\ 431 .phy_poll_interval = DT_INST_PROP(port, phy_poll_interval),\ 432 .defer_rxp_to_queue = !DT_INST_PROP(port, handle_rx_in_isr),\ 433 .defer_txd_to_queue = DT_INST_PROP(port, handle_tx_in_workq),\ 434 .amba_dbus_width = (enum eth_xlnx_amba_dbus_width)\ 435 (DT_INST_PROP(port, amba_ahb_dbus_width)),\ 436 .ahb_burst_length = (enum eth_xlnx_ahb_burst_length)\ 437 (DT_INST_PROP(port, amba_ahb_burst_length)),\ 438 .hw_rx_buffer_size = (enum eth_xlnx_hwrx_buffer_size)\ 439 (DT_INST_PROP(port, hw_rx_buffer_size)),\ 440 .hw_rx_buffer_offset = (uint8_t)\ 441 (DT_INST_PROP(port, hw_rx_buffer_offset)),\ 442 .rxbd_count = (uint8_t)\ 443 (DT_INST_PROP(port, rx_buffer_descriptors)),\ 444 .txbd_count = (uint8_t)\ 445 (DT_INST_PROP(port, tx_buffer_descriptors)),\ 446 .rx_buffer_size = (((uint16_t)(DT_INST_PROP(port, rx_buffer_size)) +\ 447 (ETH_XLNX_BUFFER_ALIGNMENT-1)) & ~(ETH_XLNX_BUFFER_ALIGNMENT-1)),\ 448 .tx_buffer_size = (((uint16_t)(DT_INST_PROP(port, tx_buffer_size)) +\ 449 (ETH_XLNX_BUFFER_ALIGNMENT-1)) & ~(ETH_XLNX_BUFFER_ALIGNMENT-1)),\ 450 .ignore_ipg_rxer = DT_INST_PROP(port, ignore_ipg_rxer),\ 451 .disable_reject_nsp = DT_INST_PROP(port, disable_reject_nsp),\ 452 .enable_ipg_stretch = DT_INST_PROP(port, ipg_stretch),\ 453 .enable_sgmii_mode = DT_INST_PROP(port, sgmii_mode),\ 454 .disable_reject_fcs_crc_errors = DT_INST_PROP(port, disable_reject_fcs_crc_errors),\ 455 .enable_rx_halfdup_while_tx = DT_INST_PROP(port, rx_halfdup_while_tx),\ 456 .enable_rx_chksum_offload = DT_INST_PROP(port, rx_checksum_offload),\ 457 .disable_pause_copy = DT_INST_PROP(port, disable_pause_copy),\ 458 .discard_rx_fcs = DT_INST_PROP(port, discard_rx_fcs),\ 459 .discard_rx_length_errors = DT_INST_PROP(port, discard_rx_length_errors),\ 460 .enable_pause = DT_INST_PROP(port, pause_frame),\ 461 .enable_tbi = DT_INST_PROP(port, tbi),\ 462 .ext_addr_match = DT_INST_PROP(port, ext_address_match),\ 463 .enable_1536_frames = DT_INST_PROP(port, long_frame_rx_support),\ 464 .enable_ucast_hash = DT_INST_PROP(port, unicast_hash),\ 465 .enable_mcast_hash = DT_INST_PROP(port, multicast_hash),\ 466 .disable_bcast = DT_INST_PROP(port, reject_broadcast),\ 467 .copy_all_frames = DT_INST_PROP(port, promiscuous_mode),\ 468 .discard_non_vlan = DT_INST_PROP(port, discard_non_vlan),\ 469 .enable_fdx = DT_INST_PROP(port, full_duplex),\ 470 .disc_rx_ahb_unavail = DT_INST_PROP(port, discard_rx_frame_ahb_unavail),\ 471 .enable_tx_chksum_offload = DT_INST_PROP(port, tx_checksum_offload),\ 472 .tx_buffer_size_full = DT_INST_PROP(port, hw_tx_buffer_size_full),\ 473 .enable_ahb_packet_endian_swap = DT_INST_PROP(port, ahb_packet_endian_swap),\ 474 .enable_ahb_md_endian_swap = DT_INST_PROP(port, ahb_md_endian_swap)\ 475 }; 476 477 /* Device run-time data declaration macro */ 478 #define ETH_XLNX_GEM_DEV_DATA(port) \ 479 static struct eth_xlnx_gem_dev_data eth_xlnx_gem##port##_dev_data = {\ 480 .mac_addr = DT_INST_PROP(port, local_mac_address),\ 481 .started = 0,\ 482 .eff_link_speed = LINK_DOWN,\ 483 .phy_addr = 0,\ 484 .phy_id = 0,\ 485 .phy_access_api = NULL,\ 486 .first_rx_buffer = NULL,\ 487 .first_tx_buffer = NULL\ 488 }; 489 490 /* DMA memory area declaration macro */ 491 #define ETH_XLNX_GEM_DMA_AREA_DECL(port) \ 492 struct eth_xlnx_dma_area_gem##port {\ 493 struct eth_xlnx_gem_bd rx_bd[DT_INST_PROP(port, rx_buffer_descriptors)];\ 494 struct eth_xlnx_gem_bd tx_bd[DT_INST_PROP(port, tx_buffer_descriptors)];\ 495 uint8_t rx_buffer\ 496 [DT_INST_PROP(port, rx_buffer_descriptors)]\ 497 [((DT_INST_PROP(port, rx_buffer_size)\ 498 + (ETH_XLNX_BUFFER_ALIGNMENT - 1))\ 499 & ~(ETH_XLNX_BUFFER_ALIGNMENT - 1))];\ 500 uint8_t tx_buffer\ 501 [DT_INST_PROP(port, tx_buffer_descriptors)]\ 502 [((DT_INST_PROP(port, tx_buffer_size)\ 503 + (ETH_XLNX_BUFFER_ALIGNMENT - 1))\ 504 & ~(ETH_XLNX_BUFFER_ALIGNMENT - 1))];\ 505 }; 506 507 /* DMA memory area instantiation macro */ 508 #define ETH_XLNX_GEM_DMA_AREA_INST(port) \ 509 static struct eth_xlnx_dma_area_gem##port eth_xlnx_gem##port##_dma_area\ 510 __ocm_bss_section __aligned(4096); 511 512 /* Interrupt configuration function macro */ 513 #define ETH_XLNX_GEM_CONFIG_IRQ_FUNC(port) \ 514 static void eth_xlnx_gem##port##_irq_config(const struct device *dev)\ 515 {\ 516 ARG_UNUSED(dev);\ 517 IRQ_CONNECT(DT_INST_IRQN(port), DT_INST_IRQ(port, priority),\ 518 eth_xlnx_gem_isr, DEVICE_DT_INST_GET(port), 0);\ 519 irq_enable(DT_INST_IRQN(port));\ 520 } 521 522 /* RX/TX BD Ring initialization macro */ 523 #define ETH_XLNX_GEM_INIT_BD_RING(port) \ 524 if (dev_conf->base_addr == DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0)) {\ 525 dev_data->rxbd_ring.first_bd = &(eth_xlnx_gem##port##_dma_area.rx_bd[0]);\ 526 dev_data->txbd_ring.first_bd = &(eth_xlnx_gem##port##_dma_area.tx_bd[0]);\ 527 dev_data->first_rx_buffer = (uint8_t *)eth_xlnx_gem##port##_dma_area.rx_buffer;\ 528 dev_data->first_tx_buffer = (uint8_t *)eth_xlnx_gem##port##_dma_area.tx_buffer;\ 529 } 530 531 /* Top-level device initialization macro - bundles all of the above */ 532 #define ETH_XLNX_GEM_INITIALIZE(port) \ 533 ETH_XLNX_GEM_CONFIG_IRQ_FUNC(port);\ 534 ETH_XLNX_GEM_DEV_CONFIG(port);\ 535 ETH_XLNX_GEM_DEV_DATA(port);\ 536 ETH_XLNX_GEM_DMA_AREA_DECL(port);\ 537 ETH_XLNX_GEM_DMA_AREA_INST(port);\ 538 ETH_XLNX_GEM_NET_DEV_INIT(port);\ 539 540 /* IRQ handler function type */ 541 typedef void (*eth_xlnx_gem_config_irq_t)(const struct device *dev); 542 543 /* Enums for bitfields representing configuration settings */ 544 545 /** 546 * @brief Link speed configuration enumeration type. 547 * 548 * Enumeration type for link speed indication, contains 'link down' 549 * plus all link speeds supported by the controller (10/100/1000). 550 */ 551 enum eth_xlnx_link_speed { 552 /* The values of this enum are consecutively numbered */ 553 LINK_DOWN = 0, 554 LINK_10MBIT, 555 LINK_100MBIT, 556 LINK_1GBIT 557 }; 558 559 /** 560 * @brief AMBA AHB data bus width configuration enumeration type. 561 * 562 * Enumeration type containing the supported width options for the 563 * AMBA AHB data bus. This is a configuration item in the controller's 564 * net_cfg register. 565 */ 566 enum eth_xlnx_amba_dbus_width { 567 /* The values of this enum are consecutively numbered */ 568 AMBA_AHB_DBUS_WIDTH_32BIT = 0, 569 AMBA_AHB_DBUS_WIDTH_64BIT, 570 AMBA_AHB_DBUS_WIDTH_128BIT 571 }; 572 573 /** 574 * @brief MDC clock divider configuration enumeration type. 575 * 576 * Enumeration type containing the supported clock divider values 577 * used to generate the MDIO interface clock (MDC) from either the 578 * cpu_1x clock (Zynq-7000) or the LPD LSBUS clock (UltraScale). 579 * This is a configuration item in the controller's net_cfg register. 580 */ 581 enum eth_xlnx_mdc_clock_divider { 582 /* The values of this enum are consecutively numbered */ 583 MDC_DIVIDER_8 = 0, 584 MDC_DIVIDER_16, 585 MDC_DIVIDER_32, 586 MDC_DIVIDER_48, 587 #ifdef CONFIG_SOC_FAMILY_XILINX_ZYNQ7000 588 /* Dividers > 48 are only available in the Zynq-7000 */ 589 MDC_DIVIDER_64, 590 MDC_DIVIDER_96, 591 MDC_DIVIDER_128, 592 MDC_DIVIDER_224 593 #endif 594 }; 595 596 /** 597 * @brief DMA RX buffer size configuration enumeration type. 598 * 599 * Enumeration type containing the supported size options for the 600 * DMA receive buffer size in AHB system memory. This is a configuration 601 * item in the controller's dma_cfg register. 602 */ 603 enum eth_xlnx_hwrx_buffer_size { 604 /* The values of this enum are consecutively numbered */ 605 HWRX_BUFFER_SIZE_1KB = 0, 606 HWRX_BUFFER_SIZE_2KB, 607 HWRX_BUFFER_SIZE_4KB, 608 HWRX_BUFFER_SIZE_8KB 609 }; 610 611 /** 612 * @brief AHB burst length configuration enumeration type. 613 * 614 * Enumeration type containing the supported burst length options 615 * for the AHB fixed burst length for DMA data operations. This is a 616 * configuration item in the controller's dma_cfg register. 617 */ 618 enum eth_xlnx_ahb_burst_length { 619 /* The values of this enum are one-hot encoded */ 620 AHB_BURST_SINGLE = 1, 621 /* 2 = also AHB_BURST_SINGLE */ 622 AHB_BURST_INCR4 = 4, 623 AHB_BURST_INCR8 = 8, 624 AHB_BURST_INCR16 = 16 625 }; 626 627 /** 628 * @brief DMA memory area buffer descriptor. 629 * 630 * An array of these descriptors for each RX and TX is used to 631 * describe the respective DMA memory area. Each address word 632 * points to the start of a RX or TX buffer within the DMA memory 633 * area, while the control word is used for buffer status exchange 634 * with the controller. 635 */ 636 struct eth_xlnx_gem_bd { 637 /* TODO for Cortex-A53: 64-bit addressing */ 638 /* TODO: timestamping support */ 639 /* Buffer physical address (absolute address) */ 640 uint32_t addr; 641 /* Buffer control word (different contents for RX and TX) */ 642 uint32_t ctrl; 643 }; 644 645 /** 646 * @brief DMA memory area buffer descriptor ring management structure. 647 * 648 * The DMA memory area buffer descriptor ring management structure 649 * is used to manage either the RX or TX buffer descriptor array 650 * (while the buffer descriptors are just an array from the software 651 * point of view, the controller treats them as a ring, in which the 652 * last descriptor's control word has a special last-in-ring bit set). 653 * It contains a pointer to the start of the descriptor array, a 654 * semaphore as a means of preventing concurrent access, a free entry 655 * counter as well as indices used to determine which BD shall be used 656 * or evaluated for the next RX/TX operation. 657 */ 658 struct eth_xlnx_gem_bdring { 659 /* Concurrent modification protection */ 660 struct k_sem ring_sem; 661 /* Pointer to the first BD in the list */ 662 struct eth_xlnx_gem_bd *first_bd; 663 /* Index of the next BD to be used for TX */ 664 uint8_t next_to_use; 665 /* Index of the next BD to be processed (both RX/TX) */ 666 uint8_t next_to_process; 667 /* Number of currently available BDs in this ring */ 668 uint8_t free_bds; 669 }; 670 671 /** 672 * @brief Constant device configuration data structure. 673 * 674 * This struct contains all device configuration data for a GEM 675 * controller instance which is constant. The data herein is 676 * either acquired from the generated header file based on the 677 * data from Kconfig, or from header file based on the device tree 678 * data. Some of the data contained, in particular data relating 679 * to clock sources, is specific to either the Zynq-7000 or the 680 * UltraScale SoCs, which both contain the GEM. 681 */ 682 struct eth_xlnx_gem_dev_cfg { 683 uint32_t base_addr; 684 eth_xlnx_gem_config_irq_t config_func; 685 686 uint32_t pll_clock_frequency; 687 uint32_t clk_ctrl_reg_address; 688 enum eth_xlnx_mdc_clock_divider mdc_divider; 689 690 enum eth_xlnx_link_speed max_link_speed; 691 bool init_phy; 692 uint8_t phy_mdio_addr_fix; 693 uint8_t phy_advertise_lower; 694 uint32_t phy_poll_interval; 695 uint8_t defer_rxp_to_queue; 696 uint8_t defer_txd_to_queue; 697 698 enum eth_xlnx_amba_dbus_width amba_dbus_width; 699 enum eth_xlnx_ahb_burst_length ahb_burst_length; 700 enum eth_xlnx_hwrx_buffer_size hw_rx_buffer_size; 701 uint8_t hw_rx_buffer_offset; 702 703 uint8_t rxbd_count; 704 uint8_t txbd_count; 705 uint16_t rx_buffer_size; 706 uint16_t tx_buffer_size; 707 708 bool ignore_ipg_rxer : 1; 709 bool disable_reject_nsp : 1; 710 bool enable_ipg_stretch : 1; 711 bool enable_sgmii_mode : 1; 712 bool disable_reject_fcs_crc_errors : 1; 713 bool enable_rx_halfdup_while_tx : 1; 714 bool enable_rx_chksum_offload : 1; 715 bool disable_pause_copy : 1; 716 bool discard_rx_fcs : 1; 717 bool discard_rx_length_errors : 1; 718 bool enable_pause : 1; 719 bool enable_tbi : 1; 720 bool ext_addr_match : 1; 721 bool enable_1536_frames : 1; 722 bool enable_ucast_hash : 1; 723 bool enable_mcast_hash : 1; 724 bool disable_bcast : 1; 725 bool copy_all_frames : 1; 726 bool discard_non_vlan : 1; 727 bool enable_fdx : 1; 728 bool disc_rx_ahb_unavail : 1; 729 bool enable_tx_chksum_offload : 1; 730 bool tx_buffer_size_full : 1; 731 bool enable_ahb_packet_endian_swap : 1; 732 bool enable_ahb_md_endian_swap : 1; 733 }; 734 735 /** 736 * @brief Run-time device configuration data structure. 737 * 738 * This struct contains all device configuration data for a GEM 739 * controller instance which is modifyable at run-time, such as 740 * data relating to the attached PHY or the auxiliary thread. 741 */ 742 struct eth_xlnx_gem_dev_data { 743 struct net_if *iface; 744 uint8_t mac_addr[6]; 745 enum eth_xlnx_link_speed eff_link_speed; 746 747 struct k_work tx_done_work; 748 struct k_work rx_pend_work; 749 struct k_sem tx_done_sem; 750 751 uint8_t phy_addr; 752 uint32_t phy_id; 753 struct k_work_delayable phy_poll_delayed_work; 754 struct phy_xlnx_gem_api *phy_access_api; 755 756 uint8_t *first_rx_buffer; 757 uint8_t *first_tx_buffer; 758 759 struct eth_xlnx_gem_bdring rxbd_ring; 760 struct eth_xlnx_gem_bdring txbd_ring; 761 762 #ifdef CONFIG_NET_STATISTICS_ETHERNET 763 struct net_stats_eth stats; 764 #endif 765 766 bool started; 767 }; 768 769 #endif /* _ZEPHYR_DRIVERS_ETHERNET_ETH_XLNX_GEM_PRIV_H_ */ 770
