1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* mbed Microcontroller Library 3 * Copyright (c) 2017 ARM Limited 4 * Copyright (c) 2018-2019 Linaro Limited 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 /* 20 * This header is originally based on mbedOS header 21 * targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h, 22 * but was considerably refactored since then. 23 */ 24 25 /* This file is the re-implementation of mps2_ethernet_api and Selftest's 26 * ETH_MPS2. 27 * MPS2 Selftest:https://silver.arm.com/browse/VEI10 -> 28 * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\ 29 */ 30 #ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC911X_PRIV_H_ 31 #define ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC911X_PRIV_H_ 32 33 #ifndef __I 34 #define __I 35 #endif 36 #ifndef __O 37 #define __O 38 #endif 39 #ifndef __IO 40 #define __IO 41 #endif 42 43 #define GET_BITFIELD(val, lsb, msb) \ 44 (((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1)) 45 #define BFIELD(val, name) GET_BITFIELD(val, name ## _Lsb, name ## _Msb) 46 #define SMSC9220_BFIELD(reg, bfield) BFIELD(SMSC9220->reg, reg ## _ ## bfield) 47 48 /******************************************************************************/ 49 /* SMSC9220 Register Definitions */ 50 /******************************************************************************/ 51 52 typedef struct { 53 /* Receive FIFO Ports (offset 0x0) */ 54 __I uint32_t RX_DATA_PORT; 55 uint32_t RESERVED1[0x7]; 56 /* Transmit FIFO Ports (offset 0x20) */ 57 __O uint32_t TX_DATA_PORT; 58 uint32_t RESERVED2[0x7]; 59 60 /* Receive FIFO status port (offset 0x40) */ 61 __I uint32_t RX_STAT_PORT; 62 /* Receive FIFO status peek (offset 0x44) */ 63 __I uint32_t RX_STAT_PEEK; 64 /* Transmit FIFO status port (offset 0x48) */ 65 __I uint32_t TX_STAT_PORT; 66 /* Transmit FIFO status peek (offset 0x4C) */ 67 __I uint32_t TX_STAT_PEEK; 68 69 /* Chip ID and Revision (offset 0x50) */ 70 __I uint32_t ID_REV; 71 /* Main Interrupt Configuration (offset 0x54) */ 72 __IO uint32_t IRQ_CFG; 73 /* Interrupt Status (offset 0x58) */ 74 __IO uint32_t INT_STS; 75 /* Interrupt Enable Register (offset 0x5C) */ 76 __IO uint32_t INT_EN; 77 /* Reserved for future use (offset 0x60) */ 78 uint32_t RESERVED3; 79 /* Read-only byte order testing register 87654321h (offset 0x64) */ 80 __I uint32_t BYTE_TEST; 81 /* FIFO Level Interrupts (offset 0x68) */ 82 __IO uint32_t FIFO_INT; 83 /* Receive Configuration (offset 0x6C) */ 84 __IO uint32_t RX_CFG; 85 /* Transmit Configuration (offset 0x70) */ 86 __IO uint32_t TX_CFG; 87 /* Hardware Configuration (offset 0x74) */ 88 __IO uint32_t HW_CFG; 89 /* RX Datapath Control (offset 0x78) */ 90 __IO uint32_t RX_DP_CTRL; 91 /* Receive FIFO Information (offset 0x7C) */ 92 __I uint32_t RX_FIFO_INF; 93 /* Transmit FIFO Information (offset 0x80) */ 94 __I uint32_t TX_FIFO_INF; 95 /* Power Management Control (offset 0x84) */ 96 __IO uint32_t PMT_CTRL; 97 /* General Purpose IO Configuration (offset 0x88) */ 98 __IO uint32_t GPIO_CFG; 99 /* General Purpose Timer Configuration (offset 0x8C) */ 100 __IO uint32_t GPT_CFG; 101 /* General Purpose Timer Count (offset 0x90) */ 102 __I uint32_t GPT_CNT; 103 /* Reserved for future use (offset 0x94) */ 104 uint32_t RESERVED4; 105 /* WORD SWAP Register (offset 0x98) */ 106 __IO uint32_t ENDIAN; 107 /* Free Run Counter (offset 0x9C) */ 108 __I uint32_t FREE_RUN; 109 /* RX Dropped Frames Counter (offset 0xA0) */ 110 __I uint32_t RX_DROP; 111 /* MAC CSR Synchronizer Command (offset 0xA4) */ 112 __IO uint32_t MAC_CSR_CMD; 113 /* MAC CSR Synchronizer Data (offset 0xA8) */ 114 __IO uint32_t MAC_CSR_DATA; 115 /* Automatic Flow Control Configuration (offset 0xAC) */ 116 __IO uint32_t AFC_CFG; 117 /* EEPROM Command (offset 0xB0) */ 118 __IO uint32_t E2P_CMD; 119 /* EEPROM Data (offset 0xB4) */ 120 __IO uint32_t E2P_DATA; 121 122 } SMSC9220_TypeDef; 123 124 #define HW_CFG_SRST BIT(0) 125 126 #define RX_STAT_PORT_PKT_LEN_Lsb 16 127 #define RX_STAT_PORT_PKT_LEN_Msb 29 128 129 #define PMT_CTRL_READY BIT(0) 130 131 #define RX_DP_CTRL_RX_FFWD BIT(31) 132 133 #define RX_FIFO_INF_RXSUSED_Lsb 16 134 #define RX_FIFO_INF_RXSUSED_Msb 23 135 #define RX_FIFO_INF_RXDUSED_Lsb 0 136 #define RX_FIFO_INF_RXDUSED_Msb 15 137 138 #define MAC_CSR_CMD_BUSY BIT(31) 139 #define MAC_CSR_CMD_READ BIT(30) 140 #define MAC_CSR_CMD_WRITE 0 141 142 /* SMSC9220 MAC Registers Indices */ 143 #define SMSC9220_MAC_CR 0x1 144 #define SMSC9220_MAC_ADDRH 0x2 145 #define SMSC9220_MAC_ADDRL 0x3 146 #define SMSC9220_MAC_HASHH 0x4 147 #define SMSC9220_MAC_HASHL 0x5 148 #define SMSC9220_MAC_MII_ACC 0x6 149 #define SMSC9220_MAC_MII_DATA 0x7 150 #define SMSC9220_MAC_FLOW 0x8 151 #define SMSC9220_MAC_VLAN1 0x9 152 #define SMSC9220_MAC_VLAN2 0xA 153 #define SMSC9220_MAC_WUFF 0xB 154 #define SMSC9220_MAC_WUCSR 0xC 155 156 #define MAC_MII_ACC_MIIBZY BIT(0) 157 #define MAC_MII_ACC_WRITE BIT(1) 158 #define MAC_MII_ACC_READ 0 159 160 /* SMSC9220 PHY Registers Indices */ 161 #define SMSC9220_PHY_BCONTROL 0 162 #define SMSC9220_PHY_BSTATUS 1 163 #define SMSC9220_PHY_ID1 2 164 #define SMSC9220_PHY_ID2 3 165 #define SMSC9220_PHY_ANEG_ADV 4 166 #define SMSC9220_PHY_ANEG_LPA 5 167 #define SMSC9220_PHY_ANEG_EXP 6 168 #define SMSC9220_PHY_MCONTROL 17 169 #define SMSC9220_PHY_MSTATUS 18 170 #define SMSC9220_PHY_CSINDICATE 27 171 #define SMSC9220_PHY_INTSRC 29 172 #define SMSC9220_PHY_INTMASK 30 173 #define SMSC9220_PHY_CS 31 174 175 #ifndef SMSC9220_BASE 176 #define SMSC9220_BASE DT_INST_REG_ADDR(0) 177 #endif 178 179 #define SMSC9220 ((volatile SMSC9220_TypeDef *)SMSC9220_BASE) 180 181 enum smsc9220_interrupt_source { 182 SMSC9220_INTERRUPT_GPIO0 = 0, 183 SMSC9220_INTERRUPT_GPIO1 = 1, 184 SMSC9220_INTERRUPT_GPIO2 = 2, 185 SMSC9220_INTERRUPT_RXSTATUS_FIFO_LEVEL = 3, 186 SMSC9220_INTERRUPT_RXSTATUS_FIFO_FULL = 4, 187 /* 5 Reserved according to Datasheet */ 188 SMSC9220_INTERRUPT_RX_DROPPED_FRAME = 6, 189 SMSC9220_INTERRUPT_TXSTATUS_FIFO_LEVEL = 7, 190 SMSC9220_INTERRUPT_TXSTATUS_FIFO_FULL = 8, 191 SMSC9220_INTERRUPT_TXDATA_FIFO_AVAILABLE = 9, 192 SMSC9220_INTERRUPT_TXDATA_FIFO_OVERRUN = 10, 193 /* 11, 12 Reserved according to Datasheet */ 194 SMSC9220_INTERRUPT_TRANSMIT_ERROR = 13, 195 SMSC9220_INTERRUPT_RECEIVE_ERROR = 14, 196 SMSC9220_INTERRUPT_RECEIVE_WATCHDOG_TIMEOUT = 15, 197 SMSC9220_INTERRUPT_TXSTATUS_OVERFLOW = 16, 198 SMSC9220_INTERRUPT_POWER_MANAGEMENT = 17, 199 SMSC9220_INTERRUPT_PHY = 18, 200 SMSC9220_INTERRUPT_GP_TIMER = 19, 201 SMSC9220_INTERRUPT_RX_DMA = 20, 202 SMSC9220_INTERRUPT_TX_IOC = 21, 203 /* 22 Reserved according to Datasheet*/ 204 SMSC9220_INTERRUPT_RX_DROPPED_FRAME_HALF = 23, 205 SMSC9220_INTERRUPT_RX_STOPPED = 24, 206 SMSC9220_INTERRUPT_TX_STOPPED = 25, 207 /* 26 - 30 Reserved according to Datasheet*/ 208 SMSC9220_INTERRUPT_SW = 31 209 }; 210 211 #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC911X_PRIV_H_ */ 212
