1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2021 Microchip Technology Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_xec_espi_v2
9
10 #include <zephyr/kernel.h>
11 #include <soc.h>
12 #include <errno.h>
13 #include <zephyr/drivers/espi.h>
14 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
15 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
16 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
17 #include <zephyr/logging/log.h>
18 #include <zephyr/sys/sys_io.h>
19 #include <zephyr/sys/util.h>
20 #include <zephyr/irq.h>
21 #include "espi_utils.h"
22 #include "espi_mchp_xec_v2.h"
23
24 /* Minimum delay before acknowledging a virtual wire */
25 #define ESPI_XEC_VWIRE_ACK_DELAY 10ul
26
27 /* Maximum timeout to transmit a virtual wire packet.
28 * 10 ms expressed in multiples of 100us
29 */
30 #define ESPI_XEC_VWIRE_SEND_TIMEOUT 100ul
31
32 #define VW_MAX_GIRQS 2ul
33
34 /* 200ms */
35 #define MAX_OOB_TIMEOUT 200ul
36 /* 1s */
37 #define MAX_FLASH_TIMEOUT 1000ul
38
39 /* While issuing flash erase command, it should be ensured that the transfer
40 * length specified is non-zero.
41 */
42 #define ESPI_FLASH_ERASE_DUMMY 0x01ul
43
44 /* OOB maximum address configuration */
45 #define ESPI_XEC_OOB_ADDR_MSW 0x1ffful
46 #define ESPI_XEC_OOB_ADDR_LSW 0xfffful
47
48 /* OOB Rx length */
49 #define ESPI_XEC_OOB_RX_LEN 0x7f00ul
50
51 /* Espi peripheral has 3 uart ports */
52 #define ESPI_PERIPHERAL_UART_PORT0 0
53 #define ESPI_PERIPHERAL_UART_PORT1 1
54
55 #define UART_DEFAULT_IRQ_POS 2u
56 #define UART_DEFAULT_IRQ BIT(UART_DEFAULT_IRQ_POS)
57
58 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
59
60 #define ESPI_XEC_REG_BASE(dev) \
61 ((struct espi_iom_regs *)ESPI_XEC_CONFIG(dev)->base_addr)
62
63 #define ESPI_XEC_MSVW_REG_BASE(dev) \
64 ((struct espi_msvw_ar_regs *)(ESPI_XEC_CONFIG(dev)->vw_base_addr))
65
66 #define ESPI_XEC_SMVW_REG_OFS 0x200
67
68 #define ESPI_XEC_SMVW_REG_BASE(dev) \
69 ((struct espi_smvw_ar_regs *) \
70 (ESPI_XEC_CONFIG(dev)->vw_base_addr + ESPI_XEC_SMVW_REG_OFS))
71
72 /* PCR */
73 #define XEC_PCR_REG_BASE \
74 ((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
75
76 /* Microchip canonical virtual wire mapping
77 * ------------------------------------------------------------------------|
78 * VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
79 * ------------------------------------------------------------------------|
80 * System Event Virtual Wires
81 * ------------------------------------------------------------------------|
82 * 2h | MSVW00 | res | SLP_S5# | SLP_S4# | SLP_S3# |
83 * 3h | MSVW01 | res | OOB_RST_WARN | PLTRST# | SUS_STAT# |
84 * 4h | SMVW00 | PME# | WAKE# | res | OOB_RST_ACK |
85 * 5h | SMVW01 | SLV_BOOT_STS | ERR_NONFATAL | ERR_FATAL | SLV_BT_DONE |
86 * 6h | SMVW02 | HOST_RST_ACK | RCIN# | SMI# | SCI# |
87 * 7h | MSVW02 | res | NMIOUT# | SMIOUT# | HOS_RST_WARN|
88 * ------------------------------------------------------------------------|
89 * Platform specific virtual wires
90 * ------------------------------------------------------------------------|
91 * 40h | SMVW03 | res | res | DNX_ACK | SUS_ACK# |
92 * 41h | MSVW03 | SLP_A# | res | SUS_PDNACK| SUS_WARN# |
93 * 42h | MSVW04 | res | res | SLP_WLAN# | SLP_LAN# |
94 * 43h | MSVW05 | generic | generic | generic | generic |
95 * 44h | MSVW06 | generic | generic | generic | generic |
96 * 45h | SMVW04 | generic | generic | generic | generic |
97 * 46h | SMVW05 | generic | generic | generic | generic |
98 * 47h | MSVW07 | res | res | res | HOST_C10 |
99 * 4Ah | MSVW08 | res | res | DNX_WARN | res |
100 * These are configurable by overriding device tree vw routing |
101 * 50h | SMVW06 | ocb_3 | ocb_2 | ocb_1 | ocb_0 |
102 * 51h | SMVW07 | gpio_7 | gpio_6 | gpio_5 | gpio_4 |
103 * 52h | SMVW08 | gpio_11 | gpio_10 | gpio_9 | gpio_8 |
104 */
105 static const struct xec_signal vw_tbl[] = {
106 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_S3, vw_slp_s3_n),
107 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_S4, vw_slp_s4_n),
108 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_S5, vw_slp_s5_n),
109 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_OOB_RST_WARN, vw_oob_rst_warn),
110 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_PLTRST, vw_pltrst_n),
111 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_STAT, vw_sus_stat_n),
112 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, vw_host_rst_warn),
113 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_NMIOUT, vw_nmiout_n),
114 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SMIOUT, vw_smiout_n),
115 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_A, vw_slp_a_n),
116 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, vw_sus_pwrdn_ack),
117 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_WARN, vw_sus_warn_n),
118 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_WLAN, vw_slp_wlan_n),
119 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_LAN, vw_slp_lan_n),
120 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_HOST_C10, vw_host_c10),
121 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_DNX_WARN, vw_dnx_warn),
122 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_PME, vw_pme_n),
123 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_WAKE, vw_wake_n),
124 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_OOB_RST_ACK, vw_oob_rst_ack),
125 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, vw_target_boot_status),
126 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, vw_error_non_fatal),
127 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_ERR_FATAL, vw_error_fatal),
128 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, vw_target_boot_done),
129 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_HOST_RST_ACK, vw_host_rst_ack),
130 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_RST_CPU_INIT, vw_rcin_n),
131 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SMI, vw_smi_n),
132 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SCI, vw_sci_n),
133 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_DNX_ACK, vw_dnx_ack),
134 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_ACK, vw_sus_ack_n),
135 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_0, vw_t2c_gpio_0),
136 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_1, vw_t2c_gpio_1),
137 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_2, vw_t2c_gpio_2),
138 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_3, vw_t2c_gpio_3),
139 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_4, vw_t2c_gpio_4),
140 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_5, vw_t2c_gpio_5),
141 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_6, vw_t2c_gpio_6),
142 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_7, vw_t2c_gpio_7),
143 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_8, vw_t2c_gpio_8),
144 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_9, vw_t2c_gpio_9),
145 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_10, vw_t2c_gpio_10),
146 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_TARGET_GPIO_11, vw_t2c_gpio_11),
147 };
148
149 /* Buffer size are expressed in bytes */
150 #ifdef CONFIG_ESPI_OOB_CHANNEL
151 static uint32_t target_rx_mem[CONFIG_ESPI_OOB_BUFFER_SIZE >> 2];
152 static uint32_t target_tx_mem[CONFIG_ESPI_OOB_BUFFER_SIZE >> 2];
153 #endif
154 #ifdef CONFIG_ESPI_FLASH_CHANNEL
155 static uint32_t target_mem[CONFIG_ESPI_FLASH_BUFFER_SIZE >> 2];
156 #endif
157
xec_msvw_addr(const struct device * dev,uint8_t vw_index)158 static inline uintptr_t xec_msvw_addr(const struct device *dev,
159 uint8_t vw_index)
160 {
161 uintptr_t vwbase = ESPI_XEC_CONFIG(dev)->vw_base_addr;
162
163 return vwbase + vw_index * sizeof(struct espi_msvw_reg);
164 }
165
xec_smvw_addr(const struct device * dev,uint8_t vw_index)166 static inline uintptr_t xec_smvw_addr(const struct device *dev,
167 uint8_t vw_index)
168 {
169 uintptr_t vwbase = ESPI_XEC_CONFIG(dev)->vw_base_addr;
170
171 vwbase += ESPI_XEC_SMVW_REG_OFS;
172 return vwbase + vw_index * sizeof(struct espi_smvw_reg);
173 }
174
espi_xec_configure(const struct device * dev,struct espi_cfg * cfg)175 static int espi_xec_configure(const struct device *dev, struct espi_cfg *cfg)
176 {
177 struct espi_iom_regs *iom_regs = ESPI_XEC_REG_BASE(dev);
178 uint8_t iomode = 0;
179 uint8_t cap0 = iom_regs->CAP0;
180 uint8_t cap1 = iom_regs->CAP1;
181 uint8_t cur_iomode = (cap1 & MCHP_ESPI_GBL_CAP1_IO_MODE_MASK) >>
182 MCHP_ESPI_GBL_CAP1_IO_MODE_POS;
183
184 /* Set frequency */
185 cap1 &= ~MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK;
186
187 switch (cfg->max_freq) {
188 case 20:
189 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M;
190 break;
191 case 25:
192 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M;
193 break;
194 case 33:
195 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M;
196 break;
197 case 50:
198 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M;
199 break;
200 case 66:
201 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M;
202 break;
203 default:
204 return -EINVAL;
205 }
206
207 /* Set IO mode */
208 iomode = (cfg->io_caps >> 1);
209 if (iomode > 3) {
210 return -EINVAL;
211 }
212
213 if (iomode != cur_iomode) {
214 cap1 &= ~(MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 <<
215 MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
216 cap1 |= (iomode << MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
217 }
218
219 /* Validate and translate eSPI API channels to MEC capabilities */
220 cap0 &= ~MCHP_ESPI_GBL_CAP0_MASK;
221 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
222 if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_CHANNEL)) {
223 cap0 |= MCHP_ESPI_GBL_CAP0_PC_SUPP;
224 } else {
225 return -EINVAL;
226 }
227 }
228
229 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
230 if (IS_ENABLED(CONFIG_ESPI_VWIRE_CHANNEL)) {
231 cap0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP;
232 } else {
233 return -EINVAL;
234 }
235 }
236
237 if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
238 if (IS_ENABLED(CONFIG_ESPI_OOB_CHANNEL)) {
239 cap0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP;
240 } else {
241 return -EINVAL;
242 }
243 }
244
245 if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
246 if (IS_ENABLED(CONFIG_ESPI_FLASH_CHANNEL)) {
247 cap0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
248 } else {
249 LOG_ERR("Flash channel not supported");
250 return -EINVAL;
251 }
252 }
253
254 iom_regs->CAP0 = cap0;
255 iom_regs->CAP1 = cap1;
256
257 /* Activate the eSPI block *.
258 * Need to guarantee that this register is configured before RSMRST#
259 * de-assertion and after pinmux
260 */
261 iom_regs->ACTV = 1;
262 LOG_DBG("eSPI block activated successfully");
263
264 return 0;
265 }
266
espi_xec_channel_ready(const struct device * dev,enum espi_channel ch)267 static bool espi_xec_channel_ready(const struct device *dev,
268 enum espi_channel ch)
269 {
270 struct espi_iom_regs *iom_regs = ESPI_XEC_REG_BASE(dev);
271 bool sts;
272
273 switch (ch) {
274 case ESPI_CHANNEL_PERIPHERAL:
275 sts = iom_regs->PCRDY & MCHP_ESPI_PC_READY;
276 break;
277 case ESPI_CHANNEL_VWIRE:
278 sts = iom_regs->VWRDY & MCHP_ESPI_VW_READY;
279 break;
280 case ESPI_CHANNEL_OOB:
281 sts = iom_regs->OOBRDY & MCHP_ESPI_OOB_READY;
282 break;
283 case ESPI_CHANNEL_FLASH:
284 sts = iom_regs->FCRDY & MCHP_ESPI_FC_READY;
285 break;
286 default:
287 sts = false;
288 break;
289 }
290
291 return sts;
292 }
293
espi_xec_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)294 static int espi_xec_send_vwire(const struct device *dev,
295 enum espi_vwire_signal signal, uint8_t level)
296 {
297 struct xec_signal signal_info = vw_tbl[signal];
298 uint8_t xec_id = signal_info.xec_reg_idx;
299 uint8_t src_id = signal_info.bit;
300 uint8_t dir;
301 uintptr_t regaddr;
302
303 if ((src_id >= ESPI_VWIRE_SRC_ID_MAX) ||
304 (xec_id >= ESPI_MSVW_IDX_MAX)) {
305 return -EINVAL;
306 }
307
308 if (!(signal_info.flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS))) {
309 return -EIO; /* VW not enabled */
310 }
311
312 dir = (signal_info.flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0);
313
314 if (dir == ESPI_CONTROLLER_TO_TARGET) {
315 regaddr = xec_msvw_addr(dev, xec_id);
316
317 sys_write8(level, regaddr + MSVW_BI_SRC0 + src_id);
318 }
319
320 if (dir == ESPI_TARGET_TO_CONTROLLER) {
321 regaddr = xec_smvw_addr(dev, xec_id);
322
323 sys_write8(level, regaddr + SMVW_BI_SRC0 + src_id);
324
325 /* Ensure eSPI virtual wire packet is transmitted
326 * There is no interrupt, so need to poll register
327 */
328 uint8_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
329
330 while (sys_read8(regaddr + SMVW_BI_SRC_CHG) && rd_cnt--) {
331 k_busy_wait(100);
332 }
333 }
334
335 return 0;
336 }
337
espi_xec_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)338 static int espi_xec_receive_vwire(const struct device *dev,
339 enum espi_vwire_signal signal,
340 uint8_t *level)
341 {
342 struct xec_signal signal_info = vw_tbl[signal];
343 uint8_t xec_id = signal_info.xec_reg_idx;
344 uint8_t src_id = signal_info.bit;
345 uint8_t dir;
346 uintptr_t regaddr;
347
348 if ((src_id >= ESPI_VWIRE_SRC_ID_MAX) ||
349 (xec_id >= ESPI_SMVW_IDX_MAX) || (level == NULL)) {
350 return -EINVAL;
351 }
352
353 if (!(signal_info.flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS))) {
354 return -EIO; /* VW not enabled */
355 }
356
357 dir = (signal_info.flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0);
358
359 if (dir == ESPI_CONTROLLER_TO_TARGET) {
360 regaddr = xec_msvw_addr(dev, xec_id);
361 *level = sys_read8(regaddr + MSVW_BI_SRC0 + src_id) & BIT(0);
362 }
363
364 if (dir == ESPI_TARGET_TO_CONTROLLER) {
365 regaddr = xec_smvw_addr(dev, xec_id);
366 *level = sys_read8(regaddr + SMVW_BI_SRC0 + src_id) & BIT(0);
367 }
368
369 return 0;
370 }
371
372 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_xec_send_oob(const struct device * dev,struct espi_oob_packet * pckt)373 static int espi_xec_send_oob(const struct device *dev,
374 struct espi_oob_packet *pckt)
375 {
376 int ret;
377 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
378 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
379 uint8_t err_mask = MCHP_ESPI_OOB_TX_STS_IBERR |
380 MCHP_ESPI_OOB_TX_STS_OVRUN |
381 MCHP_ESPI_OOB_TX_STS_BADREQ;
382
383 LOG_DBG("%s", __func__);
384
385 if (!(regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_CHEN)) {
386 LOG_ERR("OOB channel is disabled");
387 return -EIO;
388 }
389
390 if (regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_BUSY) {
391 LOG_ERR("OOB channel is busy");
392 return -EBUSY;
393 }
394
395 if (pckt->len > CONFIG_ESPI_OOB_BUFFER_SIZE) {
396 LOG_ERR("insufficient space");
397 return -EINVAL;
398 }
399
400 memcpy(target_tx_mem, pckt->buf, pckt->len);
401
402 regs->OOBTXL = pckt->len;
403 regs->OOBTXC = MCHP_ESPI_OOB_TX_CTRL_START;
404 LOG_DBG("%s %d", __func__, regs->OOBTXL);
405
406 /* Wait until ISR or timeout */
407 ret = k_sem_take(&data->tx_lock, K_MSEC(MAX_OOB_TIMEOUT));
408 if (ret == -EAGAIN) {
409 return -ETIMEDOUT;
410 }
411
412 if (regs->OOBTXSTS & err_mask) {
413 LOG_ERR("Tx failed %x", regs->OOBTXSTS);
414 regs->OOBTXSTS = err_mask;
415 return -EIO;
416 }
417
418 return 0;
419 }
420
espi_xec_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)421 static int espi_xec_receive_oob(const struct device *dev,
422 struct espi_oob_packet *pckt)
423 {
424 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
425 uint8_t err_mask = MCHP_ESPI_OOB_RX_STS_IBERR |
426 MCHP_ESPI_OOB_RX_STS_OVRUN;
427
428 if (regs->OOBRXSTS & err_mask) {
429 return -EIO;
430 }
431
432 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
433 int ret;
434 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
435
436 /* Wait until ISR or timeout */
437 ret = k_sem_take(&data->rx_lock, K_MSEC(MAX_OOB_TIMEOUT));
438 if (ret == -EAGAIN) {
439 return -ETIMEDOUT;
440 }
441 #endif
442 /* Check if buffer passed to driver can fit the received buffer */
443 uint32_t rcvd_len = regs->OOBRXL & MCHP_ESPI_OOB_RX_LEN_MASK;
444
445 if (rcvd_len > pckt->len) {
446 LOG_ERR("space rcvd %d vs %d", rcvd_len, pckt->len);
447 return -EIO;
448 }
449
450 pckt->len = rcvd_len;
451 memcpy(pckt->buf, target_rx_mem, pckt->len);
452 memset(target_rx_mem, 0, pckt->len);
453
454 /* Only after data has been copied from SRAM, indicate channel
455 * is available for next packet
456 */
457 regs->OOBRXC |= MCHP_ESPI_OOB_RX_CTRL_AVAIL;
458
459 return 0;
460 }
461 #endif /* CONFIG_ESPI_OOB_CHANNEL */
462
463 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_xec_flash_read(const struct device * dev,struct espi_flash_packet * pckt)464 static int espi_xec_flash_read(const struct device *dev,
465 struct espi_flash_packet *pckt)
466 {
467 int ret;
468 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
469 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
470 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
471 MCHP_ESPI_FC_STS_FAIL |
472 MCHP_ESPI_FC_STS_OVFL |
473 MCHP_ESPI_FC_STS_BADREQ;
474
475 LOG_DBG("%s", __func__);
476
477 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) {
478 LOG_ERR("Flash channel is disabled");
479 return -EIO;
480 }
481
482 if (pckt->len > CONFIG_ESPI_FLASH_BUFFER_SIZE) {
483 LOG_ERR("Invalid size request");
484 return -EINVAL;
485 }
486
487 regs->FCFA[1] = 0;
488 regs->FCFA[0] = pckt->flash_addr;
489 regs->FCBA[1] = 0;
490 regs->FCBA[0] = (uint32_t)&target_mem[0];
491 regs->FCLEN = pckt->len;
492 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_RD0);
493 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START;
494
495 /* Wait until ISR or timeout */
496 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
497 if (ret == -EAGAIN) {
498 LOG_ERR("%s timeout", __func__);
499 return -ETIMEDOUT;
500 }
501
502 if (regs->FCSTS & err_mask) {
503 LOG_ERR("%s error %x", __func__, err_mask);
504 regs->FCSTS = err_mask;
505 return -EIO;
506 }
507
508 memcpy(pckt->buf, target_mem, pckt->len);
509
510 return 0;
511 }
512
espi_xec_flash_write(const struct device * dev,struct espi_flash_packet * pckt)513 static int espi_xec_flash_write(const struct device *dev,
514 struct espi_flash_packet *pckt)
515 {
516 int ret;
517 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
518 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
519 MCHP_ESPI_FC_STS_OVRUN |
520 MCHP_ESPI_FC_STS_FAIL |
521 MCHP_ESPI_FC_STS_BADREQ;
522
523 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
524
525 LOG_DBG("%s", __func__);
526
527 if (sizeof(target_mem) < pckt->len) {
528 LOG_ERR("Packet length is too big");
529 return -ENOMEM;
530 }
531
532 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) {
533 LOG_ERR("Flash channel is disabled");
534 return -EIO;
535 }
536
537 if ((regs->FCCFG & MCHP_ESPI_FC_CFG_BUSY)) {
538 LOG_ERR("Flash channel is busy");
539 return -EBUSY;
540 }
541
542 memcpy(target_mem, pckt->buf, pckt->len);
543
544 regs->FCFA[1] = 0;
545 regs->FCFA[0] = pckt->flash_addr;
546 regs->FCBA[1] = 0;
547 regs->FCBA[0] = (uint32_t)&target_mem[0];
548 regs->FCLEN = pckt->len;
549 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_WR0);
550 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START;
551
552 /* Wait until ISR or timeout */
553 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
554 if (ret == -EAGAIN) {
555 LOG_ERR("%s timeout", __func__);
556 return -ETIMEDOUT;
557 }
558
559 if (regs->FCSTS & err_mask) {
560 LOG_ERR("%s err: %x", __func__, err_mask);
561 regs->FCSTS = err_mask;
562 return -EIO;
563 }
564
565 return 0;
566 }
567
espi_xec_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)568 static int espi_xec_flash_erase(const struct device *dev,
569 struct espi_flash_packet *pckt)
570 {
571 int ret;
572 uint32_t status;
573 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
574 MCHP_ESPI_FC_STS_OVRUN |
575 MCHP_ESPI_FC_STS_FAIL |
576 MCHP_ESPI_FC_STS_BADREQ;
577
578 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
579 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
580
581 LOG_DBG("%s", __func__);
582
583 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) {
584 LOG_ERR("Flash channel is disabled");
585 return -EIO;
586 }
587
588 if ((regs->FCCFG & MCHP_ESPI_FC_CFG_BUSY)) {
589 LOG_ERR("Flash channel is busy");
590 return -EBUSY;
591 }
592
593 /* Clear status register */
594 status = regs->FCSTS;
595 regs->FCSTS = status;
596
597 regs->FCFA[1] = 0;
598 regs->FCFA[0] = pckt->flash_addr;
599 regs->FCLEN = ESPI_FLASH_ERASE_DUMMY;
600 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_ERS0);
601 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START;
602
603 /* Wait until ISR or timeout */
604 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
605 if (ret == -EAGAIN) {
606 LOG_ERR("%s timeout", __func__);
607 return -ETIMEDOUT;
608 }
609
610 if (regs->FCSTS & err_mask) {
611 LOG_ERR("%s err: %x", __func__, err_mask);
612 regs->FCSTS = err_mask;
613 return -EIO;
614 }
615
616 return 0;
617 }
618 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
619
espi_xec_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)620 static int espi_xec_manage_callback(const struct device *dev,
621 struct espi_callback *callback, bool set)
622 {
623 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
624
625 return espi_manage_callback(&data->callbacks, callback, set);
626 }
627
628 #ifdef CONFIG_ESPI_AUTOMATIC_BOOT_DONE_ACKNOWLEDGE
send_slave_bootdone(const struct device * dev)629 static void send_slave_bootdone(const struct device *dev)
630 {
631 int ret;
632 uint8_t boot_done;
633
634 ret = espi_xec_receive_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE,
635 &boot_done);
636 if (!ret && !boot_done) {
637 /* SLAVE_BOOT_DONE & SLAVE_LOAD_STS have to be sent together */
638 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, 1);
639 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, 1);
640 }
641 }
642 #endif
643
644 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_init_oob(const struct device * dev)645 static void espi_init_oob(const struct device *dev)
646 {
647 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
648 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
649
650 /* Enable OOB Tx/Rx interrupts */
651 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[oob_up_girq_idx].gid,
652 cfg->irq_info_list[oob_up_girq_idx].gpos);
653 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[oob_dn_girq_idx].gid,
654 cfg->irq_info_list[oob_dn_girq_idx].gpos);
655
656 regs->OOBTXA[1] = 0;
657 regs->OOBRXA[1] = 0;
658 regs->OOBTXA[0] = (uint32_t)&target_tx_mem[0];
659 regs->OOBRXA[0] = (uint32_t)&target_rx_mem[0];
660 regs->OOBRXL = 0x00FF0000;
661
662 /* Enable OOB Tx channel enable change status interrupt */
663 regs->OOBTXIEN |= MCHP_ESPI_OOB_TX_IEN_CHG_EN |
664 MCHP_ESPI_OOB_TX_IEN_DONE;
665
666 /* Enable Rx channel to receive data any time
667 * there are case where OOB is not initiated by a previous OOB Tx
668 */
669 regs->OOBRXIEN |= MCHP_ESPI_OOB_RX_IEN;
670 regs->OOBRXC |= MCHP_ESPI_OOB_RX_CTRL_AVAIL;
671 }
672 #endif
673
674 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_init_flash(const struct device * dev)675 static void espi_init_flash(const struct device *dev)
676 {
677 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
678 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
679
680 LOG_DBG("%s", __func__);
681
682 /* Need to clear status done when ROM boots in MAF */
683 LOG_DBG("%s ESPI_FC_REGS->CFG %X", __func__, regs->FCCFG);
684 regs->FCSTS = MCHP_ESPI_FC_STS_DONE;
685
686 /* Enable interrupts */
687 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[fc_girq_idx].gid,
688 cfg->irq_info_list[fc_girq_idx].gpos);
689 regs->FCIEN |= MCHP_ESPI_FC_IEN_CHG_EN;
690 regs->FCIEN |= MCHP_ESPI_FC_IEN_DONE;
691 }
692 #endif
693
espi_bus_init(const struct device * dev)694 static void espi_bus_init(const struct device *dev)
695 {
696 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
697
698 /* Enable bus interrupts */
699 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[pc_girq_idx].gid,
700 cfg->irq_info_list[pc_girq_idx].gpos);
701 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[rst_girq_idx].gid,
702 cfg->irq_info_list[rst_girq_idx].gpos);
703 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[vw_ch_en_girq_idx].gid,
704 cfg->irq_info_list[vw_ch_en_girq_idx].gpos);
705 }
706
707 /* Clear specified eSPI bus GIRQ status */
xec_espi_bus_intr_clr(const struct device * dev,enum xec_espi_girq_idx idx)708 static int xec_espi_bus_intr_clr(const struct device *dev,
709 enum xec_espi_girq_idx idx)
710 {
711 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
712
713 if (idx >= max_girq_idx) {
714 return -EINVAL;
715 }
716
717 mchp_xec_ecia_girq_src_clr(cfg->irq_info_list[idx].gid,
718 cfg->irq_info_list[idx].gpos);
719
720 return 0;
721 }
722
723 /* Enable/disable specified eSPI bus GIRQ */
xec_espi_bus_intr_ctl(const struct device * dev,enum xec_espi_girq_idx idx,uint8_t enable)724 static int xec_espi_bus_intr_ctl(const struct device *dev,
725 enum xec_espi_girq_idx idx,
726 uint8_t enable)
727 {
728 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
729
730 if (idx >= max_girq_idx) {
731 return -EINVAL;
732 }
733
734 if (enable) {
735 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[idx].gid,
736 cfg->irq_info_list[idx].gpos);
737 } else {
738 mchp_xec_ecia_girq_src_dis(cfg->irq_info_list[idx].gid,
739 cfg->irq_info_list[idx].gpos);
740 }
741
742 return 0;
743 }
744
espi_rst_isr(const struct device * dev)745 static void espi_rst_isr(const struct device *dev)
746 {
747 uint8_t rst_sts;
748 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
749 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
750 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
751
752 #ifdef ESPI_XEC_V2_DEBUG
753 data->espi_rst_count++;
754 #endif
755
756 rst_sts = regs->ERIS;
757
758 /* eSPI reset status register is clear on write register */
759 regs->ERIS = MCHP_ESPI_RST_ISTS;
760 /* clear GIRQ latched status */
761 xec_espi_bus_intr_clr(dev, rst_girq_idx);
762
763 if (rst_sts & MCHP_ESPI_RST_ISTS) {
764 if (rst_sts & MCHP_ESPI_RST_ISTS_PIN_RO_HI) {
765 evt.evt_data = 1;
766 } else {
767 evt.evt_data = 0;
768 }
769
770 espi_send_callbacks(&data->callbacks, dev, evt);
771 #ifdef CONFIG_ESPI_OOB_CHANNEL
772 espi_init_oob(dev);
773 #endif
774 #ifdef CONFIG_ESPI_FLASH_CHANNEL
775 espi_init_flash(dev);
776 #endif
777 espi_bus_init(dev);
778 }
779 }
780
781 /* Configure sub devices BAR address if not using default I/O based address
782 * then make its BAR valid.
783 * Refer to microchip eSPI I/O base addresses for default values
784 */
config_sub_devices(const struct device * dev)785 static void config_sub_devices(const struct device *dev)
786 {
787 xec_host_dev_init(dev);
788 }
789
configure_sirq(const struct device * dev)790 static void configure_sirq(const struct device *dev)
791 {
792 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
793
794 #ifdef CONFIG_ESPI_PERIPHERAL_UART
795 switch (CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING) {
796 case ESPI_PERIPHERAL_UART_PORT0:
797 regs->SIRQ[SIRQ_UART0] = UART_DEFAULT_IRQ;
798 break;
799 case ESPI_PERIPHERAL_UART_PORT1:
800 regs->SIRQ[SIRQ_UART1] = UART_DEFAULT_IRQ;
801 break;
802 }
803 #endif
804 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
805 regs->SIRQ[SIRQ_KBC_KIRQ] = 1;
806 regs->SIRQ[SIRQ_KBC_MIRQ] = 12;
807 #endif
808 }
809
setup_espi_io_config(const struct device * dev,uint16_t host_address)810 static void setup_espi_io_config(const struct device *dev,
811 uint16_t host_address)
812 {
813 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
814
815 regs->IOHBAR[IOB_IOC] = (host_address << 16) |
816 MCHP_ESPI_IO_BAR_HOST_VALID;
817
818 config_sub_devices(dev);
819 configure_sirq(dev);
820
821 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG |
822 MCHP_ESPI_PC_STS_BM_EN_CHG_POS;
823 regs->PCIEN |= MCHP_ESPI_PC_IEN_EN_CHG;
824 regs->PCRDY = 1;
825 }
826
827 /*
828 * Write the interrupt select field of the specified MSVW source.
829 * Each MSVW controls 4 virtual wires.
830 */
xec_espi_vw_intr_ctrl(const struct device * dev,uint8_t msvw_idx,uint8_t src_id,uint8_t intr_mode)831 static int xec_espi_vw_intr_ctrl(const struct device *dev, uint8_t msvw_idx,
832 uint8_t src_id, uint8_t intr_mode)
833 {
834 struct espi_msvw_ar_regs *regs = ESPI_XEC_MSVW_REG_BASE(dev);
835
836
837 if ((msvw_idx >= ESPI_NUM_MSVW) || (src_id > 3)) {
838 return -EINVAL;
839 }
840
841 uintptr_t msvw_addr = (uintptr_t)®s->MSVW[msvw_idx];
842
843 sys_write8(intr_mode, msvw_addr + MSVW_BI_IRQ_SEL0 + src_id);
844
845 return 0;
846 }
847
espi_pc_isr(const struct device * dev)848 static void espi_pc_isr(const struct device *dev)
849 {
850 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
851 uint32_t status = regs->PCSTS;
852 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
853 .evt_details = ESPI_CHANNEL_PERIPHERAL,
854 .evt_data = 0 };
855 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
856
857 LOG_DBG("%s %x", __func__, status);
858 if (status & MCHP_ESPI_PC_STS_BUS_ERR) {
859 LOG_ERR("%s bus error", __func__);
860 regs->PCSTS = MCHP_ESPI_PC_STS_BUS_ERR;
861 }
862
863 if (status & MCHP_ESPI_PC_STS_EN_CHG) {
864 if (status & MCHP_ESPI_PC_STS_EN) {
865 setup_espi_io_config(dev, MCHP_ESPI_IOBAR_INIT_DFLT);
866 }
867
868 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG;
869 }
870
871 if (status & MCHP_ESPI_PC_STS_BM_EN_CHG) {
872 if (status & MCHP_ESPI_PC_STS_BM_EN) {
873 evt.evt_data = ESPI_PC_EVT_BUS_MASTER_ENABLE;
874 LOG_WRN("%s BM change %x", __func__, status);
875 espi_send_callbacks(&data->callbacks, dev, evt);
876 }
877
878 regs->PCSTS = MCHP_ESPI_PC_STS_BM_EN_CHG;
879 }
880
881 xec_espi_bus_intr_clr(dev, pc_girq_idx);
882 }
883
espi_vw_chan_en_isr(const struct device * dev)884 static void espi_vw_chan_en_isr(const struct device *dev)
885 {
886 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
887 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
888 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
889 .evt_details = ESPI_CHANNEL_VWIRE,
890 .evt_data = 0 };
891 uint32_t status = regs->VWSTS;
892
893 if (status & MCHP_ESPI_VW_EN_STS_RO) {
894 regs->VWRDY = 1;
895 evt.evt_data = 1;
896 /* VW channel interrupt can disabled at this point */
897 xec_espi_bus_intr_ctl(dev, vw_ch_en_girq_idx, 0);
898
899 #ifdef CONFIG_ESPI_AUTOMATIC_BOOT_DONE_ACKNOWLEDGE
900 send_slave_bootdone(dev);
901 #endif
902 }
903
904 espi_send_callbacks(&data->callbacks, dev, evt);
905
906 xec_espi_bus_intr_clr(dev, vw_ch_en_girq_idx);
907 }
908
909 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_oob_down_isr(const struct device * dev)910 static void espi_oob_down_isr(const struct device *dev)
911 {
912 uint32_t status;
913 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
914 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
915 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
916 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
917 .evt_details = 0,
918 .evt_data = 0 };
919 #endif
920
921 status = regs->OOBRXSTS;
922
923 LOG_DBG("%s %x", __func__, status);
924 if (status & MCHP_ESPI_OOB_RX_STS_DONE) {
925 /* Register is write-on-clear, ensure only 1 bit is affected */
926 regs->OOBRXSTS = MCHP_ESPI_OOB_RX_STS_DONE;
927
928 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
929 k_sem_give(&data->rx_lock);
930 #else
931 evt.evt_details = regs->OOBRXL &
932 MCHP_ESPI_OOB_RX_LEN_MASK;
933 espi_send_callbacks(&data->callbacks, dev, evt);
934 #endif
935 }
936
937 xec_espi_bus_intr_clr(dev, oob_dn_girq_idx);
938 }
939
espi_oob_up_isr(const struct device * dev)940 static void espi_oob_up_isr(const struct device *dev)
941 {
942 uint32_t status;
943 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
944 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
945 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
946 .evt_details = ESPI_CHANNEL_OOB,
947 .evt_data = 0
948 };
949
950 status = regs->OOBTXSTS;
951 LOG_DBG("%s sts:%x", __func__, status);
952
953 if (status & MCHP_ESPI_OOB_TX_STS_DONE) {
954 /* Register is write-on-clear, ensure only 1 bit is affected */
955 status = regs->OOBTXSTS = MCHP_ESPI_OOB_TX_STS_DONE;
956 k_sem_give(&data->tx_lock);
957 }
958
959 if (status & MCHP_ESPI_OOB_TX_STS_CHG_EN) {
960 if (status & MCHP_ESPI_OOB_TX_STS_CHEN) {
961 espi_init_oob(dev);
962 /* Indicate OOB channel is ready to eSPI host */
963 regs->OOBRDY = 1;
964 evt.evt_data = 1;
965 }
966
967 status = regs->OOBTXSTS = MCHP_ESPI_OOB_TX_STS_CHG_EN;
968 espi_send_callbacks(&data->callbacks, dev, evt);
969 }
970
971 xec_espi_bus_intr_clr(dev, oob_up_girq_idx);
972 }
973 #endif
974
975 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_flash_isr(const struct device * dev)976 static void espi_flash_isr(const struct device *dev)
977 {
978 uint32_t status;
979 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
980 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
981 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
982 .evt_details = ESPI_CHANNEL_FLASH,
983 .evt_data = 0,
984 };
985
986 status = regs->FCSTS;
987 LOG_DBG("%s %x", __func__, status);
988
989 if (status & MCHP_ESPI_FC_STS_DONE) {
990 /* Ensure to clear only relevant bit */
991 regs->FCSTS = MCHP_ESPI_FC_STS_DONE;
992
993 k_sem_give(&data->flash_lock);
994 }
995
996 if (status & MCHP_ESPI_FC_STS_CHAN_EN_CHG) {
997 /* Ensure to clear only relevant bit */
998 regs->FCSTS = MCHP_ESPI_FC_STS_CHAN_EN_CHG;
999
1000 if (status & MCHP_ESPI_FC_STS_CHAN_EN) {
1001 espi_init_flash(dev);
1002 /* Indicate flash channel is ready to eSPI master */
1003 regs->FCRDY = MCHP_ESPI_FC_READY;
1004 evt.evt_data = 1;
1005 }
1006
1007 espi_send_callbacks(&data->callbacks, dev, evt);
1008 }
1009
1010 xec_espi_bus_intr_clr(dev, fc_girq_idx);
1011 }
1012 #endif
1013
1014 /* Send callbacks if enabled and track eSPI host system state */
notify_system_state(const struct device * dev,enum espi_vwire_signal signal)1015 static void notify_system_state(const struct device *dev,
1016 enum espi_vwire_signal signal)
1017 {
1018 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1019 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1020 uint8_t status = 0;
1021
1022 espi_xec_receive_vwire(dev, signal, &status);
1023 evt.evt_details = signal;
1024 evt.evt_data = status;
1025 espi_send_callbacks(&data->callbacks, dev, evt);
1026 }
1027
notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)1028 static void notify_host_warning(const struct device *dev,
1029 enum espi_vwire_signal signal)
1030 {
1031 uint8_t status;
1032
1033 espi_xec_receive_vwire(dev, signal, &status);
1034
1035 if (!IS_ENABLED(CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE)) {
1036 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1037 struct espi_event evt = {ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1038
1039 evt.evt_details = signal;
1040 evt.evt_data = status;
1041 espi_send_callbacks(&data->callbacks, dev, evt);
1042 } else {
1043 k_busy_wait(ESPI_XEC_VWIRE_ACK_DELAY);
1044 /* Some flows are dependent on awareness of client's driver
1045 * about these warnings in such cases these automatic response
1046 * should not be enabled.
1047 */
1048 switch (signal) {
1049 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
1050 espi_xec_send_vwire(dev,
1051 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
1052 status);
1053 break;
1054 case ESPI_VWIRE_SIGNAL_SUS_WARN:
1055 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
1056 status);
1057 break;
1058 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
1059 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
1060 status);
1061 break;
1062 case ESPI_VWIRE_SIGNAL_DNX_WARN:
1063 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_DNX_ACK,
1064 status);
1065 break;
1066 default:
1067 break;
1068 }
1069 }
1070 }
1071
notify_vw_status(const struct device * dev,enum espi_vwire_signal signal)1072 static void notify_vw_status(const struct device *dev,
1073 enum espi_vwire_signal signal)
1074 {
1075 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1076 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1077 uint8_t status = 0;
1078
1079 espi_xec_receive_vwire(dev, signal, &status);
1080 evt.evt_details = signal;
1081 evt.evt_data = status;
1082 espi_send_callbacks(&data->callbacks, dev, evt);
1083 }
1084
1085 /*
1086 * VW handlers must have signature
1087 * typedef void (*mchp_xec_ecia_callback_t) (int girq_id, int src, void *user)
1088 * where parameter user is a pointer to const struct device
1089 * These handlers are registered to their respective GIRQ child device of the
1090 * ECIA driver.
1091 */
1092
vw_slp3_handler(int girq_id,int src,void * user)1093 static void vw_slp3_handler(int girq_id, int src, void *user)
1094 {
1095 const struct device *dev = (const struct device *)user;
1096
1097 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S3);
1098 }
1099
vw_slp4_handler(int girq_id,int src,void * user)1100 static void vw_slp4_handler(int girq_id, int src, void *user)
1101 {
1102 const struct device *dev = (const struct device *)user;
1103
1104 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S4);
1105 }
1106
vw_slp5_handler(int girq_id,int src,void * user)1107 static void vw_slp5_handler(int girq_id, int src, void *user)
1108 {
1109 const struct device *dev = (const struct device *)user;
1110
1111 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S5);
1112 }
1113
vw_host_rst_warn_handler(int girq_id,int src,void * user)1114 static void vw_host_rst_warn_handler(int girq_id, int src, void *user)
1115 {
1116 const struct device *dev = (const struct device *)user;
1117
1118 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_HOST_RST_WARN);
1119 }
1120
vw_sus_warn_handler(int girq_id,int src,void * user)1121 static void vw_sus_warn_handler(int girq_id, int src, void *user)
1122 {
1123 const struct device *dev = (const struct device *)user;
1124
1125 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_SUS_WARN);
1126 }
1127
vw_oob_rst_handler(int girq_id,int src,void * user)1128 static void vw_oob_rst_handler(int girq_id, int src, void *user)
1129 {
1130 const struct device *dev = (const struct device *)user;
1131
1132 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_OOB_RST_WARN);
1133 }
1134
vw_sus_pwrdn_ack_handler(int girq_id,int src,void * user)1135 static void vw_sus_pwrdn_ack_handler(int girq_id, int src, void *user)
1136 {
1137 const struct device *dev = (const struct device *)user;
1138
1139 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK);
1140 }
1141
vw_sus_slp_a_handler(int girq_id,int src,void * user)1142 static void vw_sus_slp_a_handler(int girq_id, int src, void *user)
1143 {
1144 const struct device *dev = (const struct device *)user;
1145
1146 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SLP_A);
1147 }
1148
vw_sus_dnx_warn_handler(int girq_id,int src,void * user)1149 static void vw_sus_dnx_warn_handler(int girq_id, int src, void *user)
1150 {
1151 const struct device *dev = (const struct device *)user;
1152
1153 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_DNX_WARN);
1154 }
1155
vw_pltrst_handler(int girq_id,int src,void * user)1156 static void vw_pltrst_handler(int girq_id, int src, void *user)
1157 {
1158 const struct device *dev = (const struct device *)user;
1159 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1160 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
1161 ESPI_VWIRE_SIGNAL_PLTRST, 0
1162 };
1163 uint8_t status = 0;
1164
1165 espi_xec_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &status);
1166 if (status) {
1167 setup_espi_io_config(dev, MCHP_ESPI_IOBAR_INIT_DFLT);
1168 }
1169
1170 evt.evt_data = status;
1171 espi_send_callbacks(&data->callbacks, dev, evt);
1172 }
1173
vw_sus_stat_handler(int girq_id,int src,void * user)1174 static void vw_sus_stat_handler(int girq_id, int src, void *user)
1175 {
1176 const struct device *dev = (const struct device *)user;
1177
1178 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_SUS_STAT);
1179 }
1180
vw_slp_wlan_handler(int girq_id,int src,void * user)1181 static void vw_slp_wlan_handler(int girq_id, int src, void *user)
1182 {
1183 const struct device *dev = (const struct device *)user;
1184
1185 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SLP_WLAN);
1186 }
1187
vw_slp_lan_handler(int girq_id,int src,void * user)1188 static void vw_slp_lan_handler(int girq_id, int src, void *user)
1189 {
1190 const struct device *dev = (const struct device *)user;
1191
1192 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SLP_LAN);
1193 }
1194
vw_host_c10_handler(int girq_id,int src,void * user)1195 static void vw_host_c10_handler(int girq_id, int src, void *user)
1196 {
1197 const struct device *dev = (const struct device *)user;
1198
1199 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_HOST_C10);
1200 }
1201
vw_nmiout_handler(int girq_id,int src,void * user)1202 static void vw_nmiout_handler(int girq_id, int src, void *user)
1203 {
1204 const struct device *dev = (const struct device *)user;
1205
1206 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_NMIOUT);
1207 }
1208
vw_smiout_handler(int girq_id,int src,void * user)1209 static void vw_smiout_handler(int girq_id, int src, void *user)
1210 {
1211 const struct device *dev = (const struct device *)user;
1212
1213 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SMIOUT);
1214 }
1215
1216 const struct espi_vw_isr m2s_vwires_isr[] = {
1217 {ESPI_VWIRE_SIGNAL_SLP_S3, MCHP_MSVW00_GIRQ,
1218 MCHP_MSVW00_SRC0_GIRQ_POS, vw_slp3_handler},
1219 {ESPI_VWIRE_SIGNAL_SLP_S4, MCHP_MSVW00_GIRQ,
1220 MCHP_MSVW00_SRC1_GIRQ_POS, vw_slp4_handler},
1221 {ESPI_VWIRE_SIGNAL_SLP_S5, MCHP_MSVW00_GIRQ,
1222 MCHP_MSVW00_SRC2_GIRQ_POS, vw_slp5_handler},
1223 {ESPI_VWIRE_SIGNAL_OOB_RST_WARN, MCHP_MSVW01_GIRQ,
1224 MCHP_MSVW01_SRC2_GIRQ_POS, vw_oob_rst_handler},
1225 {ESPI_VWIRE_SIGNAL_PLTRST, MCHP_MSVW01_GIRQ,
1226 MCHP_MSVW01_SRC1_GIRQ_POS, vw_pltrst_handler},
1227 {ESPI_VWIRE_SIGNAL_SUS_STAT, MCHP_MSVW01_GIRQ,
1228 MCHP_MSVW01_SRC0_GIRQ_POS, vw_sus_stat_handler},
1229 {ESPI_VWIRE_SIGNAL_HOST_RST_WARN, MCHP_MSVW02_GIRQ,
1230 MCHP_MSVW02_SRC0_GIRQ_POS, vw_host_rst_warn_handler},
1231 {ESPI_VWIRE_SIGNAL_NMIOUT, MCHP_MSVW02_GIRQ,
1232 MCHP_MSVW02_SRC1_GIRQ_POS, vw_nmiout_handler},
1233 {ESPI_VWIRE_SIGNAL_SMIOUT, MCHP_MSVW02_GIRQ,
1234 MCHP_MSVW02_SRC2_GIRQ_POS, vw_smiout_handler},
1235 {ESPI_VWIRE_SIGNAL_SLP_A, MCHP_MSVW03_GIRQ,
1236 MCHP_MSVW03_SRC3_GIRQ_POS, vw_sus_slp_a_handler},
1237 {ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, MCHP_MSVW03_GIRQ,
1238 MCHP_MSVW03_SRC1_GIRQ_POS, vw_sus_pwrdn_ack_handler},
1239 {ESPI_VWIRE_SIGNAL_SUS_WARN, MCHP_MSVW03_GIRQ,
1240 MCHP_MSVW03_SRC0_GIRQ_POS, vw_sus_warn_handler},
1241 {ESPI_VWIRE_SIGNAL_SLP_WLAN, MCHP_MSVW04_GIRQ,
1242 MCHP_MSVW04_SRC1_GIRQ_POS, vw_slp_wlan_handler},
1243 {ESPI_VWIRE_SIGNAL_SLP_LAN, MCHP_MSVW04_GIRQ,
1244 MCHP_MSVW04_SRC0_GIRQ_POS, vw_slp_lan_handler},
1245 {ESPI_VWIRE_SIGNAL_HOST_C10, MCHP_MSVW07_GIRQ,
1246 MCHP_MSVW07_SRC0_GIRQ_POS, vw_host_c10_handler},
1247 {ESPI_VWIRE_SIGNAL_DNX_WARN, MCHP_MSVW08_GIRQ,
1248 MCHP_MSVW08_SRC1_GIRQ_POS, vw_sus_dnx_warn_handler},
1249 };
1250
1251 static int espi_xec_init(const struct device *dev);
1252
1253 static const struct espi_driver_api espi_xec_driver_api = {
1254 .config = espi_xec_configure,
1255 .get_channel_status = espi_xec_channel_ready,
1256 .send_vwire = espi_xec_send_vwire,
1257 .receive_vwire = espi_xec_receive_vwire,
1258 #ifdef CONFIG_ESPI_OOB_CHANNEL
1259 .send_oob = espi_xec_send_oob,
1260 .receive_oob = espi_xec_receive_oob,
1261 #endif
1262 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1263 .flash_read = espi_xec_flash_read,
1264 .flash_write = espi_xec_flash_write,
1265 .flash_erase = espi_xec_flash_erase,
1266 #endif
1267 .manage_callback = espi_xec_manage_callback,
1268 .read_lpc_request = espi_xec_read_lpc_request,
1269 .write_lpc_request = espi_xec_write_lpc_request,
1270 };
1271
1272 static struct espi_xec_data espi_xec_data_var;
1273
1274 /* n = node-id, p = property, i = index */
1275 #define XEC_IRQ_INFO(n, p, i) \
1276 { \
1277 .gid = MCHP_XEC_ECIA_GIRQ(DT_PROP_BY_IDX(n, p, i)), \
1278 .gpos = MCHP_XEC_ECIA_GIRQ_POS(DT_PROP_BY_IDX(n, p, i)), \
1279 .anid = MCHP_XEC_ECIA_NVIC_AGGR(DT_PROP_BY_IDX(n, p, i)), \
1280 .dnid = MCHP_XEC_ECIA_NVIC_DIRECT(DT_PROP_BY_IDX(n, p, i)), \
1281 },
1282
1283 static const struct espi_xec_irq_info espi_xec_irq_info_0[] = {
1284 DT_FOREACH_PROP_ELEM(DT_NODELABEL(espi0), girqs, XEC_IRQ_INFO)
1285 };
1286
1287 /* pin control structure(s) */
1288 PINCTRL_DT_INST_DEFINE(0);
1289
1290 static const struct espi_xec_config espi_xec_config = {
1291 .base_addr = DT_INST_REG_ADDR(0),
1292 .vw_base_addr = DT_INST_REG_ADDR_BY_NAME(0, vw),
1293 .pcr_idx = DT_INST_PROP_BY_IDX(0, pcrs, 0),
1294 .pcr_bitpos = DT_INST_PROP_BY_IDX(0, pcrs, 1),
1295 .irq_info_size = ARRAY_SIZE(espi_xec_irq_info_0),
1296 .irq_info_list = espi_xec_irq_info_0,
1297 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1298 };
1299
1300 DEVICE_DT_INST_DEFINE(0, &espi_xec_init, NULL,
1301 &espi_xec_data_var, &espi_xec_config,
1302 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1303 &espi_xec_driver_api);
1304
1305 /*
1306 * Connect ESPI bus interrupt handlers: ESPI_RESET and channels.
1307 * MEC172x hardware fixed SAF interrupt routing bug. SAF driver
1308 * will connect its direct mode interrupt handler(s) on this GIRQ.
1309 */
espi_xec_connect_irqs(const struct device * dev)1310 static void espi_xec_connect_irqs(const struct device *dev)
1311 {
1312 ARG_UNUSED(dev);
1313
1314 /* eSPI Reset */
1315 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 7, irq),
1316 DT_INST_IRQ_BY_IDX(0, 7, priority),
1317 espi_rst_isr,
1318 DEVICE_DT_INST_GET(0), 0);
1319 irq_enable(DT_INST_IRQ_BY_IDX(0, 7, irq));
1320
1321 /* eSPI Virtual wire channel enable change ISR */
1322 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 8, irq),
1323 DT_INST_IRQ_BY_IDX(0, 8, priority),
1324 espi_vw_chan_en_isr,
1325 DEVICE_DT_INST_GET(0), 0);
1326 irq_enable(DT_INST_IRQ_BY_IDX(0, 8, irq));
1327
1328 /* eSPI Peripheral Channel */
1329 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 0, irq),
1330 DT_INST_IRQ_BY_IDX(0, 0, priority),
1331 espi_pc_isr,
1332 DEVICE_DT_INST_GET(0), 0);
1333 irq_enable(DT_INST_IRQ_BY_IDX(0, 0, irq));
1334
1335 #ifdef CONFIG_ESPI_OOB_CHANNEL
1336 /* eSPI OOB Upstream direction */
1337 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 4, irq),
1338 DT_INST_IRQ_BY_IDX(0, 4, priority),
1339 espi_oob_up_isr,
1340 DEVICE_DT_INST_GET(0), 0);
1341 irq_enable(DT_INST_IRQ_BY_IDX(0, 4, irq));
1342
1343 /* eSPI OOB Channel Downstream direction */
1344 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 5, irq),
1345 DT_INST_IRQ_BY_IDX(0, 5, priority),
1346 espi_oob_down_isr,
1347 DEVICE_DT_INST_GET(0), 0);
1348 irq_enable(DT_INST_IRQ_BY_IDX(0, 5, irq));
1349 #endif
1350
1351 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1352 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 6, irq),
1353 DT_INST_IRQ_BY_IDX(0, 6, priority),
1354 espi_flash_isr,
1355 DEVICE_DT_INST_GET(0), 0);
1356 irq_enable(DT_INST_IRQ_BY_IDX(0, 6, irq));
1357 #endif
1358 }
1359
1360 /* MSVW is a 96-bit register and SMVW is a 64-bit register.
1361 * Each MSVW/SMVW controls a group of 4 eSPI virtual wires.
1362 * Host index located in b[7:0]
1363 * Reset source located in b[9:8]
1364 * Reset VW values SRC[3:0] located in b[15:12].
1365 * MSVW current VW state values located in bits[64, 72, 80, 88]
1366 * SMVW current VW state values located in bits[32, 40, 48, 56]
1367 */
xec_vw_cfg_properties(const struct xec_signal * p,uint32_t regaddr,uint8_t dir)1368 static void xec_vw_cfg_properties(const struct xec_signal *p, uint32_t regaddr, uint8_t dir)
1369 {
1370 uint32_t src_ofs = 4u;
1371 uint8_t src_pos = (8u * p->bit);
1372 uint8_t rst_state = (p->flags >> MCHP_DT_ESPI_VW_FLAG_RST_STATE_POS)
1373 & MCHP_DT_ESPI_VW_FLAG_RST_STATE_MSK0;
1374 uint8_t rst_src = rst_src = (p->flags >> MCHP_DT_ESPI_VW_FLAG_RST_SRC_POS)
1375 & MCHP_DT_ESPI_VW_FLAG_RST_SRC_MSK0;
1376
1377 if (dir) {
1378 src_ofs = 8u;
1379 }
1380
1381 if (rst_state || rst_src) { /* change reset source or state ? */
1382 sys_write8(0, regaddr); /* disable register */
1383
1384 uint8_t temp = sys_read8(regaddr + 1u);
1385
1386 if (rst_state) { /* change reset state and default value of this vwire? */
1387 rst_state--;
1388 if (rst_state) {
1389 temp |= BIT(p->bit + 4u);
1390 sys_set_bit(regaddr + src_ofs, src_pos);
1391 } else {
1392 temp |= ~BIT(p->bit + 4u);
1393 sys_clear_bit(regaddr + src_ofs, src_pos);
1394 }
1395 }
1396
1397 if (rst_src) { /* change reset source of all vwires in this group? */
1398 rst_src--;
1399 temp = (temp & ~0x3u) | (rst_src & 0x3u);
1400 }
1401
1402 sys_write8(temp, regaddr + 1u);
1403 }
1404
1405 if (sys_read8(regaddr) != p->host_idx) {
1406 sys_write8(p->host_idx, regaddr);
1407 }
1408 }
1409
1410 /* Check each VW register set host index is present.
1411 * Some VW's power up with the host index and others do not.
1412 * NOTE: Virtual wires are in groups of 4. Disabling one wire in a group
1413 * will disable all wires in the group. We do not implement disabling.
1414 */
xec_vw_config(const struct device * dev)1415 static void xec_vw_config(const struct device *dev)
1416 {
1417 for (int i = ESPI_VWIRE_SIGNAL_TARGET_GPIO_0; i < ARRAY_SIZE(vw_tbl); i++) {
1418 const struct xec_signal *p = &vw_tbl[i];
1419 uint32_t regaddr = xec_smvw_addr(dev, p->xec_reg_idx);
1420 uint8_t dir = (p->flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0);
1421 uint8_t en = (p->flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS));
1422
1423 if (dir) {
1424 regaddr = xec_msvw_addr(dev, p->xec_reg_idx);
1425 }
1426
1427 if (en) {
1428 xec_vw_cfg_properties(p, regaddr, dir);
1429 }
1430 }
1431 }
1432
xec_register_vw_handlers(const struct device * dev)1433 static int xec_register_vw_handlers(const struct device *dev)
1434 {
1435 for (int i = 0; i < ARRAY_SIZE(m2s_vwires_isr); i++) {
1436 const struct espi_vw_isr *vwi = &m2s_vwires_isr[i];
1437 struct xec_signal signal_info = vw_tbl[vwi->signal];
1438 uint8_t xec_id = signal_info.xec_reg_idx;
1439 uint8_t en = (signal_info.flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS));
1440
1441 if (!en) {
1442 LOG_INF("VW %d not enabled, skipping", vwi->signal);
1443 continue;
1444 }
1445
1446 /* enables interrupt in eSPI MSVWn register */
1447 xec_espi_vw_intr_ctrl(dev, xec_id, signal_info.bit,
1448 MSVW_IRQ_SEL_EDGE_BOTH);
1449
1450 /* register handler */
1451 int ret = mchp_xec_ecia_set_callback(vwi->girq_id, vwi->girq_pos,
1452 vwi->the_isr, (void *)dev);
1453 if (ret) {
1454 return -EIO;
1455 }
1456
1457 mchp_xec_ecia_girq_src_en(vwi->girq_id, vwi->girq_pos);
1458 }
1459
1460 return 0;
1461 }
1462
1463 /*
1464 * Initialize eSPI hardware and associated peripherals blocks using eSPI
1465 * as their host interface.
1466 * We change VW capabilities reported to match the number of VWires the
1467 * driver is supporting.
1468 * A VW packet on the bus contains VW count followed by the VW groups.
1469 * The VW count is a zero based 6-bit value: (0 - 63) specifying the number of
1470 * groups in the packet.
1471 * A VW group consists of two bytes: VW host index and VW data. Each group
1472 * contains the state of 4 virtual wires.
1473 * The total supported virtual wires is 64 * 4 = 256.
1474 * MEC172x supports 11 MSVW groups and 11 SMVW groups.
1475 * NOTE: While ESPI_nRESET is active most of the eSPI hardware is held
1476 * in reset state.
1477 */
espi_xec_init(const struct device * dev)1478 static int espi_xec_init(const struct device *dev)
1479 {
1480 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
1481 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
1482 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1483 struct pcr_regs *pcr = XEC_PCR_REG_BASE;
1484 int ret;
1485
1486 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
1487 if (ret != 0) {
1488 LOG_ERR("XEC eSPI V2 pinctrl setup failed (%d)", ret);
1489 return ret;
1490 }
1491
1492 #ifdef ESPI_XEC_V2_DEBUG
1493 data->espi_rst_count = 0;
1494 #endif
1495 /* clear eSPI PCR sleep enable */
1496 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_bitpos, 0);
1497
1498 /* Configure eSPI_PLTRST# to cause nSIO_RESET reset
1499 * NOTE: this is also clearing bit 0(PWR_INV) causing the internal
1500 * RESET_VCC to de-assert. Host facing peripherals will no longer
1501 * be held in reset.
1502 */
1503 pcr->PWR_RST_CTRL = MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST;
1504 regs->PLTSRC = MCHP_ESPI_PLTRST_SRC_IS_VW;
1505
1506 /* Configure the channels and its capabilities based on build config */
1507 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP | MCHP_ESPI_GBL_CAP0_PC_SUPP;
1508
1509 regs->CAPVW = MAX(ESPI_NUM_MSVW, ESPI_NUM_SMVW);
1510 regs->CAPPC |= MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64;
1511
1512 #ifdef CONFIG_ESPI_OOB_CHANNEL
1513 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP;
1514 regs->CAPOOB |= MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73;
1515
1516 k_sem_init(&data->tx_lock, 0, 1);
1517 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1518 k_sem_init(&data->rx_lock, 0, 1);
1519 #endif /* CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC */
1520 #else
1521 regs->CAP0 &= ~MCHP_ESPI_GBL_CAP0_OOB_SUPP;
1522 #endif
1523
1524 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1525 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP |
1526 MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64;
1527 regs->CAPFC |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF |
1528 MCHP_ESPI_FC_CAP_MAX_RD_SZ_64;
1529
1530 k_sem_init(&data->flash_lock, 0, 1);
1531 #else
1532 regs->CAP0 &= ~MCHP_ESPI_GBL_CAP0_FC_SUPP;
1533 #endif
1534
1535 /* Clear reset interrupt status and enable interrupts */
1536 regs->ERIS = MCHP_ESPI_RST_ISTS;
1537 regs->ERIE |= MCHP_ESPI_RST_IEN;
1538 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG;
1539 regs->PCIEN |= MCHP_ESPI_PC_IEN_EN_CHG;
1540
1541 xec_vw_config(dev);
1542
1543 /* register VWire handlers with their aggregated GIRQs
1544 * in the ECIA driver
1545 */
1546 ret = xec_register_vw_handlers(dev);
1547 if (ret) {
1548 LOG_ERR("XEX eSPI V2 register VW handlers error %d", ret);
1549 return ret;
1550 }
1551
1552 /* Enable interrupts for each logical channel enable assertion */
1553 xec_espi_bus_intr_ctl(dev, pc_girq_idx, 1);
1554 xec_espi_bus_intr_ctl(dev, vw_ch_en_girq_idx, 1);
1555 xec_espi_bus_intr_ctl(dev, rst_girq_idx, 1);
1556
1557 #ifdef CONFIG_ESPI_OOB_CHANNEL
1558 espi_init_oob(dev);
1559 #endif
1560 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1561 espi_init_flash(dev);
1562 #endif
1563
1564 espi_xec_connect_irqs(dev);
1565
1566 ret = xec_host_dev_connect_irqs(dev);
1567
1568 return ret;
1569 }
1570
