1 /*
2 * Copyright (c) 2018 Kokoon Technology Limited
3 * Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
4 * Copyright (c) 2019 Endre Karlson
5 * Copyright (c) 2020 Teslabs Engineering S.L.
6 * Copyright (c) 2021 Marius Scholtz, RIC Electronics
7 * Copyright (c) 2023 Hein Wessels, Nobleo Technology
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 */
11
12 #define DT_DRV_COMPAT st_stm32_adc
13
14 #include <errno.h>
15
16 #include <zephyr/drivers/adc.h>
17 #include <zephyr/drivers/pinctrl.h>
18 #include <zephyr/device.h>
19 #include <zephyr/kernel.h>
20 #include <zephyr/init.h>
21 #include <soc.h>
22 #include <zephyr/pm/device.h>
23 #include <zephyr/pm/policy.h>
24 #include <stm32_ll_adc.h>
25 #include <stm32_ll_system.h>
26 #if defined(CONFIG_SOC_SERIES_STM32U5X)
27 #include <stm32_ll_pwr.h>
28 #endif /* CONFIG_SOC_SERIES_STM32U5X */
29
30 #ifdef CONFIG_ADC_STM32_DMA
31 #include <zephyr/drivers/dma/dma_stm32.h>
32 #include <zephyr/drivers/dma.h>
33 #include <zephyr/toolchain.h>
34 #include <stm32_ll_dma.h>
35 #endif
36
37 #define ADC_CONTEXT_USES_KERNEL_TIMER
38 #define ADC_CONTEXT_ENABLE_ON_COMPLETE
39 #include "adc_context.h"
40
41 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
42 #include <zephyr/logging/log.h>
43 LOG_MODULE_REGISTER(adc_stm32);
44
45 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
46 #include <zephyr/dt-bindings/adc/stm32_adc.h>
47 #include <zephyr/irq.h>
48 #include <zephyr/mem_mgmt/mem_attr.h>
49
50 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H7RSX)
51 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
52 #endif
53
54 #ifdef CONFIG_NOCACHE_MEMORY
55 #include <zephyr/linker/linker-defs.h>
56 #elif defined(CONFIG_CACHE_MANAGEMENT)
57 #include <zephyr/arch/cache.h>
58 #endif /* CONFIG_NOCACHE_MEMORY */
59
60 #if defined(CONFIG_SOC_SERIES_STM32F3X)
61 #if defined(ADC1_V2_5)
62 /* ADC1_V2_5 is the ADC version for STM32F37x */
63 #define STM32F3X_ADC_V2_5
64 #elif defined(ADC5_V1_1)
65 /* ADC5_V1_1 is the ADC version for other STM32F3x */
66 #define STM32F3X_ADC_V1_1
67 #endif
68 #endif
69 /*
70 * Other ADC versions:
71 * ADC_VER_V5_V90 -> STM32H72x/H73x
72 * ADC_VER_V5_X -> STM32H74x/H75x && U5
73 * ADC_VER_V5_3 -> STM32H7Ax/H7Bx
74 * compat st_stm32f1_adc -> STM32F1, F37x (ADC1_V2_5)
75 * compat st_stm32f4_adc -> STM32F2, F4, F7, L1
76 */
77
78 #define ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(value) \
79 (DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_PROP_OR, \
80 num_sampling_time_common_channels,\
81 0, value) 0)
82
83 #define ANY_ADC_SEQUENCER_TYPE_IS(value) \
84 (DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_PROP_OR, \
85 st_adc_sequencer,\
86 0, value) 0)
87
88 #define IS_EQ_PROP_OR(inst, prop, default_value, compare_value) \
89 IS_EQ(DT_INST_PROP_OR(inst, prop, default_value), compare_value) ||
90
91 /* reference voltage for the ADC */
92 #define STM32_ADC_VREF_MV DT_INST_PROP(0, vref_mv)
93
94 #if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
95 #define RANK(n) LL_ADC_REG_RANK_##n
96 static const uint32_t table_rank[] = {
97 RANK(1),
98 RANK(2),
99 RANK(3),
100 RANK(4),
101 RANK(5),
102 RANK(6),
103 RANK(7),
104 RANK(8),
105 RANK(9),
106 RANK(10),
107 RANK(11),
108 RANK(12),
109 RANK(13),
110 RANK(14),
111 RANK(15),
112 RANK(16),
113 #if defined(LL_ADC_REG_RANK_17)
114 RANK(17),
115 RANK(18),
116 RANK(19),
117 RANK(20),
118 RANK(21),
119 RANK(22),
120 RANK(23),
121 RANK(24),
122 RANK(25),
123 RANK(26),
124 RANK(27),
125 #if defined(LL_ADC_REG_RANK_28)
126 RANK(28),
127 #endif /* LL_ADC_REG_RANK_28 */
128 #endif /* LL_ADC_REG_RANK_17 */
129 };
130
131 #define SEQ_LEN(n) LL_ADC_REG_SEQ_SCAN_ENABLE_##n##RANKS
132 /* Length of this array signifies the maximum sequence length */
133 static const uint32_t table_seq_len[] = {
134 LL_ADC_REG_SEQ_SCAN_DISABLE,
135 SEQ_LEN(2),
136 SEQ_LEN(3),
137 SEQ_LEN(4),
138 SEQ_LEN(5),
139 SEQ_LEN(6),
140 SEQ_LEN(7),
141 SEQ_LEN(8),
142 SEQ_LEN(9),
143 SEQ_LEN(10),
144 SEQ_LEN(11),
145 SEQ_LEN(12),
146 SEQ_LEN(13),
147 SEQ_LEN(14),
148 SEQ_LEN(15),
149 SEQ_LEN(16),
150 #if defined(LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS)
151 SEQ_LEN(17),
152 SEQ_LEN(18),
153 SEQ_LEN(19),
154 SEQ_LEN(20),
155 SEQ_LEN(21),
156 SEQ_LEN(22),
157 SEQ_LEN(23),
158 SEQ_LEN(24),
159 SEQ_LEN(25),
160 SEQ_LEN(26),
161 SEQ_LEN(27),
162 #if defined(LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS)
163 SEQ_LEN(28),
164 #endif /* LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS */
165 #endif /* LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS */
166 };
167 #endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
168
169 /* Number of different sampling time values */
170 #define STM32_NB_SAMPLING_TIME 8
171
172 #ifdef CONFIG_ADC_STM32_DMA
173 struct stream {
174 const struct device *dma_dev;
175 uint32_t channel;
176 struct dma_config dma_cfg;
177 struct dma_block_config dma_blk_cfg;
178 uint8_t priority;
179 bool src_addr_increment;
180 bool dst_addr_increment;
181 };
182 #endif /* CONFIG_ADC_STM32_DMA */
183
184 struct adc_stm32_data {
185 struct adc_context ctx;
186 const struct device *dev;
187 uint16_t *buffer;
188 uint16_t *repeat_buffer;
189
190 uint8_t resolution;
191 uint32_t channels;
192 uint8_t channel_count;
193 uint8_t samples_count;
194 int8_t acq_time_index[2];
195
196 #ifdef CONFIG_ADC_STM32_DMA
197 volatile int dma_error;
198 struct stream dma;
199 #endif
200 };
201
202 struct adc_stm32_cfg {
203 ADC_TypeDef *base;
204 void (*irq_cfg_func)(void);
205 const struct stm32_pclken *pclken;
206 size_t pclk_len;
207 uint32_t clk_prescaler;
208 const struct pinctrl_dev_config *pcfg;
209 const uint16_t sampling_time_table[STM32_NB_SAMPLING_TIME];
210 int8_t num_sampling_time_common_channels;
211 int8_t sequencer_type;
212 int8_t res_table_size;
213 const uint32_t res_table[];
214 };
215
216 #ifdef CONFIG_ADC_STM32_DMA
adc_stm32_enable_dma_support(ADC_TypeDef * adc)217 static void adc_stm32_enable_dma_support(ADC_TypeDef *adc)
218 {
219 /* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */
220
221 #if defined(CONFIG_SOC_SERIES_STM32H7X)
222
223 #if defined(ADC_VER_V5_V90)
224 if (adc == ADC3) {
225 LL_ADC_REG_SetDMATransferMode(adc, LL_ADC3_REG_DMA_TRANSFER_LIMITED);
226 } else {
227 LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED);
228 }
229 #elif defined(ADC_VER_V5_X)
230 LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED);
231 #else
232 #error "Unsupported ADC version"
233 #endif
234
235 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) /* defined(CONFIG_SOC_SERIES_STM32H7X) */
236
237 #error "The STM32F1 ADC + DMA is not yet supported"
238
239 #elif defined(CONFIG_SOC_SERIES_STM32U5X) /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
240
241 if (adc == ADC4) {
242 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4);
243 } else {
244 LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED);
245 }
246
247 #else /* defined(CONFIG_SOC_SERIES_STM32U5X) */
248
249 /* Default mechanism for other MCUs */
250 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED);
251
252 #endif
253 }
254
adc_stm32_dma_start(const struct device * dev,void * buffer,size_t channel_count)255 static int adc_stm32_dma_start(const struct device *dev,
256 void *buffer, size_t channel_count)
257 {
258 const struct adc_stm32_cfg *config = dev->config;
259 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
260 struct adc_stm32_data *data = dev->data;
261 struct dma_block_config *blk_cfg;
262 int ret;
263
264 struct stream *dma = &data->dma;
265
266 blk_cfg = &dma->dma_blk_cfg;
267
268 /* prepare the block */
269 blk_cfg->block_size = channel_count * sizeof(int16_t);
270
271 /* Source and destination */
272 blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA);
273 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
274 blk_cfg->source_reload_en = 0;
275
276 blk_cfg->dest_address = (uint32_t)buffer;
277 blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
278 blk_cfg->dest_reload_en = 0;
279
280 /* Manually set the FIFO threshold to 1/4 because the
281 * dmamux DTS entry does not contain fifo threshold
282 */
283 blk_cfg->fifo_mode_control = 0;
284
285 /* direction is given by the DT */
286 dma->dma_cfg.head_block = blk_cfg;
287 dma->dma_cfg.user_data = data;
288
289 ret = dma_config(data->dma.dma_dev, data->dma.channel,
290 &dma->dma_cfg);
291 if (ret != 0) {
292 LOG_ERR("Problem setting up DMA: %d", ret);
293 return ret;
294 }
295
296 adc_stm32_enable_dma_support(adc);
297
298 data->dma_error = 0;
299 ret = dma_start(data->dma.dma_dev, data->dma.channel);
300 if (ret != 0) {
301 LOG_ERR("Problem starting DMA: %d", ret);
302 return ret;
303 }
304
305 LOG_DBG("DMA started");
306
307 return ret;
308 }
309 #endif /* CONFIG_ADC_STM32_DMA */
310
311 #if defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X)
312 /* Returns true if given buffer is in a non-cacheable SRAM region.
313 * This is determined using the device tree, meaning the .nocache region won't work.
314 * The entire buffer must be in a single region.
315 * An example of how the SRAM region can be defined in the DTS:
316 * &sram4 {
317 * zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) | ... )>;
318 * };
319 */
buf_in_nocache(uintptr_t buf,size_t len_bytes)320 static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
321 {
322 bool buf_within_nocache = false;
323
324 #ifdef CONFIG_NOCACHE_MEMORY
325 buf_within_nocache = (buf >= ((uintptr_t)_nocache_ram_start)) &&
326 ((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end));
327 if (buf_within_nocache) {
328 return true;
329 }
330 #endif /* CONFIG_NOCACHE_MEMORY */
331
332 buf_within_nocache = mem_attr_check_buf(
333 (void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
334
335 return buf_within_nocache;
336 }
337 #endif /* defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X) */
338
check_buffer(const struct adc_sequence * sequence,uint8_t active_channels)339 static int check_buffer(const struct adc_sequence *sequence,
340 uint8_t active_channels)
341 {
342 size_t needed_buffer_size;
343
344 needed_buffer_size = active_channels * sizeof(uint16_t);
345
346 if (sequence->options) {
347 needed_buffer_size *= (1 + sequence->options->extra_samplings);
348 }
349
350 if (sequence->buffer_size < needed_buffer_size) {
351 LOG_ERR("Provided buffer is too small (%u/%u)",
352 sequence->buffer_size, needed_buffer_size);
353 return -ENOMEM;
354 }
355
356 #if defined(CONFIG_ADC_STM32_DMA) && defined(CONFIG_SOC_SERIES_STM32H7X)
357 /* Buffer is forced to be in non-cacheable SRAM region to avoid cache maintenance */
358 if (!buf_in_nocache((uintptr_t)sequence->buffer, needed_buffer_size)) {
359 LOG_ERR("Supplied buffer is not in a non-cacheable region according to DTS.");
360 return -EINVAL;
361 }
362 #endif
363
364 return 0;
365 }
366
367 /*
368 * Enable ADC peripheral, and wait until ready if required by SOC.
369 */
adc_stm32_enable(ADC_TypeDef * adc)370 static int adc_stm32_enable(ADC_TypeDef *adc)
371 {
372 if (LL_ADC_IsEnabled(adc) == 1UL) {
373 return 0;
374 }
375
376 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
377 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
378 LL_ADC_ClearFlag_ADRDY(adc);
379 LL_ADC_Enable(adc);
380
381 /*
382 * Enabling ADC modules in many series may fail if they are
383 * still not stabilized, this will wait for a short time (about 1ms)
384 * to ensure ADC modules are properly enabled.
385 */
386 uint32_t count_timeout = 0;
387
388 while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {
389 #ifdef CONFIG_SOC_SERIES_STM32F0X
390 /* For F0, continue to write ADEN=1 until ADRDY=1 */
391 if (LL_ADC_IsEnabled(adc) == 0UL) {
392 LL_ADC_Enable(adc);
393 }
394 #endif /* CONFIG_SOC_SERIES_STM32F0X */
395 count_timeout++;
396 k_busy_wait(100);
397 if (count_timeout >= 10) {
398 return -ETIMEDOUT;
399 }
400 }
401 #else
402 /*
403 * On STM32F1, F2, F37x, F4, F7 and L1, do not re-enable the ADC.
404 * On F1 and F37x if ADON holds 1 (LL_ADC_IsEnabled is true) and 1 is
405 * written, then conversion starts. That's not what is expected.
406 */
407 LL_ADC_Enable(adc);
408 #endif
409
410 return 0;
411 }
412
adc_stm32_start_conversion(const struct device * dev)413 static void adc_stm32_start_conversion(const struct device *dev)
414 {
415 const struct adc_stm32_cfg *config = dev->config;
416 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
417
418 LOG_DBG("Starting conversion");
419
420 #if !defined(CONFIG_SOC_SERIES_STM32F1X) && \
421 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
422 LL_ADC_REG_StartConversion(adc);
423 #else
424 LL_ADC_REG_StartConversionSWStart(adc);
425 #endif
426 }
427
428 /*
429 * Disable ADC peripheral, and wait until it is disabled
430 */
adc_stm32_disable(ADC_TypeDef * adc)431 static void adc_stm32_disable(ADC_TypeDef *adc)
432 {
433 if (LL_ADC_IsEnabled(adc) != 1UL) {
434 return;
435 }
436
437 /* Stop ongoing conversion if any
438 * Software must poll ADSTART (or JADSTART) until the bit is reset before assuming
439 * the ADC is completely stopped.
440 */
441
442 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
443 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
444 if (LL_ADC_REG_IsConversionOngoing(adc)) {
445 LL_ADC_REG_StopConversion(adc);
446 while (LL_ADC_REG_IsConversionOngoing(adc)) {
447 }
448 }
449 #endif
450
451 #if !defined(CONFIG_SOC_SERIES_STM32C0X) && \
452 !defined(CONFIG_SOC_SERIES_STM32F0X) && \
453 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
454 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \
455 !defined(CONFIG_SOC_SERIES_STM32G0X) && \
456 !defined(CONFIG_SOC_SERIES_STM32L0X) && \
457 !defined(CONFIG_SOC_SERIES_STM32WBAX) && \
458 !defined(CONFIG_SOC_SERIES_STM32WLX)
459 if (LL_ADC_INJ_IsConversionOngoing(adc)) {
460 LL_ADC_INJ_StopConversion(adc);
461 while (LL_ADC_INJ_IsConversionOngoing(adc)) {
462 }
463 }
464 #endif
465
466 LL_ADC_Disable(adc);
467
468 /* Wait ADC is fully disabled so that we don't leave the driver into intermediate state
469 * which could prevent enabling the peripheral
470 */
471 while (LL_ADC_IsEnabled(adc) == 1UL) {
472 }
473 }
474
475 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
476
477 #define HAS_CALIBRATION
478
479 /* Number of ADC clock cycles to wait before of after starting calibration */
480 #if defined(LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES)
481 #define ADC_DELAY_CALIB_ADC_CYCLES LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES
482 #elif defined(LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES)
483 #define ADC_DELAY_CALIB_ADC_CYCLES LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES
484 #elif defined(LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES)
485 #define ADC_DELAY_CALIB_ADC_CYCLES LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES
486 #endif
487
adc_stm32_calibration_delay(const struct device * dev)488 static void adc_stm32_calibration_delay(const struct device *dev)
489 {
490 /*
491 * Calibration of F1 and F3 (ADC1_V2_5) must start two cycles after ADON
492 * is set.
493 * Other ADC modules have to wait for some cycles after calibration to
494 * be enabled.
495 */
496 const struct adc_stm32_cfg *config = dev->config;
497 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
498 uint32_t adc_rate, wait_cycles;
499
500 if (clock_control_get_rate(clk,
501 (clock_control_subsys_t) &config->pclken[0], &adc_rate) < 0) {
502 LOG_ERR("ADC clock rate get error.");
503 }
504
505 if (adc_rate == 0) {
506 LOG_ERR("ADC Clock rate null");
507 return;
508 }
509 wait_cycles = SystemCoreClock / adc_rate *
510 ADC_DELAY_CALIB_ADC_CYCLES;
511
512 for (int i = wait_cycles; i >= 0; i--) {
513 }
514 }
515
adc_stm32_calibration_start(const struct device * dev)516 static void adc_stm32_calibration_start(const struct device *dev)
517 {
518 const struct adc_stm32_cfg *config =
519 (const struct adc_stm32_cfg *)dev->config;
520 ADC_TypeDef *adc = config->base;
521
522 #if defined(STM32F3X_ADC_V1_1) || \
523 defined(CONFIG_SOC_SERIES_STM32L4X) || \
524 defined(CONFIG_SOC_SERIES_STM32L5X) || \
525 defined(CONFIG_SOC_SERIES_STM32H5X) || \
526 defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
527 defined(CONFIG_SOC_SERIES_STM32WBX) || \
528 defined(CONFIG_SOC_SERIES_STM32G4X)
529 LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
530 #elif defined(CONFIG_SOC_SERIES_STM32C0X) || \
531 defined(CONFIG_SOC_SERIES_STM32F0X) || \
532 DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \
533 defined(CONFIG_SOC_SERIES_STM32G0X) || \
534 defined(CONFIG_SOC_SERIES_STM32L0X) || \
535 defined(CONFIG_SOC_SERIES_STM32WLX) || \
536 defined(CONFIG_SOC_SERIES_STM32WBAX)
537 LL_ADC_StartCalibration(adc);
538 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
539 if (adc != ADC4) {
540 uint32_t dev_id = LL_DBGMCU_GetDeviceID();
541 uint32_t rev_id = LL_DBGMCU_GetRevisionID();
542
543 /* Some U5 implement an extended calibration to enhance ADC performance.
544 * It is not available for ADC4.
545 * It is available on all U5 except U575/585 (dev ID 482) revision X (rev ID 2001).
546 * The code below applies the procedure described in RM0456 in the ADC chapter:
547 * "Extended calibration mode"
548 */
549 if ((dev_id != 0x482UL) && (rev_id != 0x2001UL)) {
550 adc_stm32_enable(adc);
551 MODIFY_REG(adc->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos);
552 MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);
553 SET_BIT(adc->CALFACT, ADC_CALFACT_LATCH_COEF);
554 adc_stm32_disable(adc);
555 }
556 }
557 LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET);
558 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
559 LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED);
560 #endif
561 /* Make sure ADCAL is cleared before returning for proper operations
562 * on the ADC control register, for enabling the peripheral for example
563 */
564 while (LL_ADC_IsCalibrationOnGoing(adc)) {
565 }
566 }
567
adc_stm32_calibrate(const struct device * dev)568 static int adc_stm32_calibrate(const struct device *dev)
569 {
570 const struct adc_stm32_cfg *config =
571 (const struct adc_stm32_cfg *)dev->config;
572 ADC_TypeDef *adc = config->base;
573 int err;
574
575 #if defined(CONFIG_ADC_STM32_DMA)
576 #if defined(CONFIG_SOC_SERIES_STM32C0X) || \
577 defined(CONFIG_SOC_SERIES_STM32F0X) || \
578 defined(CONFIG_SOC_SERIES_STM32G0X) || \
579 defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
580 defined(CONFIG_SOC_SERIES_STM32L0X) || \
581 defined(CONFIG_SOC_SERIES_STM32WBAX) || \
582 defined(CONFIG_SOC_SERIES_STM32WLX)
583 /* Make sure DMA is disabled before starting calibration */
584 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE);
585 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
586 if (adc == ADC4) {
587 /* Make sure DMA is disabled before starting calibration */
588 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE);
589 }
590 #endif /* CONFIG_SOC_SERIES_* */
591 #endif /* CONFIG_ADC_STM32_DMA */
592
593 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
594 adc_stm32_disable(adc);
595 adc_stm32_calibration_start(dev);
596 adc_stm32_calibration_delay(dev);
597 #endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
598
599 err = adc_stm32_enable(adc);
600 if (err < 0) {
601 return err;
602 }
603
604 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
605 adc_stm32_calibration_delay(dev);
606 adc_stm32_calibration_start(dev);
607 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
608
609 #if defined(CONFIG_SOC_SERIES_STM32H7X) && \
610 defined(CONFIG_CPU_CORTEX_M7)
611 /*
612 * To ensure linearity the factory calibration values
613 * should be loaded on initialization.
614 */
615 uint32_t channel_offset = 0U;
616 uint32_t linear_calib_buffer = 0U;
617
618 if (adc == ADC1) {
619 channel_offset = 0UL;
620 } else if (adc == ADC2) {
621 channel_offset = 8UL;
622 } else /*Case ADC3*/ {
623 channel_offset = 16UL;
624 }
625 /* Read factory calibration factors */
626 for (uint32_t count = 0UL; count < ADC_LINEAR_CALIB_REG_COUNT; count++) {
627 linear_calib_buffer = *(uint32_t *)(
628 ADC_LINEAR_CALIB_REG_1_ADDR + channel_offset + count
629 );
630
631 LL_ADC_SetCalibrationLinearFactor(
632 adc, LL_ADC_CALIB_LINEARITY_WORD1 << count,
633 linear_calib_buffer
634 );
635 }
636 #endif /* CONFIG_SOC_SERIES_STM32H7X */
637
638 return 0;
639 }
640 #endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) */
641
642 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
643 !defined(CONFIG_SOC_SERIES_STM32F1X) && \
644 !defined(CONFIG_SOC_SERIES_STM32F3X) && \
645 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
646
647 #define HAS_OVERSAMPLING
648
649 #define OVS_SHIFT(n) LL_ADC_OVS_SHIFT_RIGHT_##n
650 static const uint32_t table_oversampling_shift[] = {
651 LL_ADC_OVS_SHIFT_NONE,
652 OVS_SHIFT(1),
653 OVS_SHIFT(2),
654 OVS_SHIFT(3),
655 OVS_SHIFT(4),
656 OVS_SHIFT(5),
657 OVS_SHIFT(6),
658 OVS_SHIFT(7),
659 OVS_SHIFT(8),
660 #if defined(CONFIG_SOC_SERIES_STM32H7X) || \
661 defined(CONFIG_SOC_SERIES_STM32U5X)
662 OVS_SHIFT(9),
663 OVS_SHIFT(10),
664 #endif
665 };
666
667 #ifdef LL_ADC_OVS_RATIO_2
668 #define OVS_RATIO(n) LL_ADC_OVS_RATIO_##n
669 static const uint32_t table_oversampling_ratio[] = {
670 0,
671 OVS_RATIO(2),
672 OVS_RATIO(4),
673 OVS_RATIO(8),
674 OVS_RATIO(16),
675 OVS_RATIO(32),
676 OVS_RATIO(64),
677 OVS_RATIO(128),
678 OVS_RATIO(256),
679 };
680 #endif
681
682 /*
683 * Function to configure the oversampling scope. It is basically a wrapper over
684 * LL_ADC_SetOverSamplingScope() which in addition stops the ADC if needed.
685 */
adc_stm32_oversampling_scope(ADC_TypeDef * adc,uint32_t ovs_scope)686 static void adc_stm32_oversampling_scope(ADC_TypeDef *adc, uint32_t ovs_scope)
687 {
688 #if defined(CONFIG_SOC_SERIES_STM32G0X) || \
689 defined(CONFIG_SOC_SERIES_STM32L0X) || \
690 defined(CONFIG_SOC_SERIES_STM32WLX)
691 /*
692 * Setting OVS bits is conditioned to ADC state: ADC must be disabled
693 * or enabled without conversion on going : disable it, it will stop.
694 * For the G0 series, ADC must be disabled to prevent CKMODE bitfield
695 * from getting reset, see errata ES0418 section 2.6.4.
696 */
697 if (LL_ADC_GetOverSamplingScope(adc) == ovs_scope) {
698 return;
699 }
700 adc_stm32_disable(adc);
701 #endif
702 LL_ADC_SetOverSamplingScope(adc, ovs_scope);
703 }
704
705 /*
706 * Function to configure the oversampling ratio and shift. It is basically a
707 * wrapper over LL_ADC_SetOverSamplingRatioShift() which in addition stops the
708 * ADC if needed.
709 */
adc_stm32_oversampling_ratioshift(ADC_TypeDef * adc,uint32_t ratio,uint32_t shift)710 static void adc_stm32_oversampling_ratioshift(ADC_TypeDef *adc, uint32_t ratio, uint32_t shift)
711 {
712 /*
713 * setting OVS bits is conditioned to ADC state: ADC must be disabled
714 * or enabled without conversion on going : disable it, it will stop
715 */
716 if ((LL_ADC_GetOverSamplingRatio(adc) == ratio)
717 && (LL_ADC_GetOverSamplingShift(adc) == shift)) {
718 return;
719 }
720 adc_stm32_disable(adc);
721
722 LL_ADC_ConfigOverSamplingRatioShift(adc, ratio, shift);
723 }
724
725 /*
726 * Function to configure the oversampling ratio and shift using stm32 LL
727 * ratio is directly the sequence->oversampling (a 2^n value)
728 * shift is the corresponding LL_ADC_OVS_SHIFT_RIGHT_x constant
729 */
adc_stm32_oversampling(ADC_TypeDef * adc,uint8_t ratio)730 static int adc_stm32_oversampling(ADC_TypeDef *adc, uint8_t ratio)
731 {
732 if (ratio == 0) {
733 adc_stm32_oversampling_scope(adc, LL_ADC_OVS_DISABLE);
734 return 0;
735 } else if (ratio < ARRAY_SIZE(table_oversampling_shift)) {
736 adc_stm32_oversampling_scope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
737 } else {
738 LOG_ERR("Invalid oversampling");
739 return -EINVAL;
740 }
741
742 uint32_t shift = table_oversampling_shift[ratio];
743
744 #if defined(CONFIG_SOC_SERIES_STM32H7X)
745 /* Certain variants of the H7, such as STM32H72x/H73x has ADC3
746 * as a separate entity and require special handling.
747 */
748 #if defined(ADC_VER_V5_V90)
749 if (adc != ADC3) {
750 /* the LL function expects a value from 1 to 1024 */
751 adc_stm32_oversampling_ratioshift(adc, 1 << ratio, shift);
752 } else {
753 /* the LL function expects a value LL_ADC_OVS_RATIO_x */
754 adc_stm32_oversampling_ratioshift(adc, table_oversampling_ratio[ratio], shift);
755 }
756 #else
757 /* the LL function expects a value from 1 to 1024 */
758 adc_stm32_oversampling_ratioshift(adc, 1 << ratio, shift);
759 #endif /* defined(ADC_VER_V5_V90) */
760 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
761 if (adc != ADC4) {
762 /* the LL function expects a value from 1 to 1024 */
763 adc_stm32_oversampling_ratioshift(adc, (1 << ratio), shift);
764 } else {
765 /* the LL function expects a value LL_ADC_OVS_RATIO_x */
766 adc_stm32_oversampling_ratioshift(adc, table_oversampling_ratio[ratio], shift);
767 }
768 #else /* CONFIG_SOC_SERIES_STM32H7X */
769 adc_stm32_oversampling_ratioshift(adc, table_oversampling_ratio[ratio], shift);
770 #endif /* CONFIG_SOC_SERIES_STM32H7X */
771
772 return 0;
773 }
774 #endif /* CONFIG_SOC_SERIES_STM32xxx */
775
776 #ifdef CONFIG_ADC_STM32_DMA
dma_callback(const struct device * dev,void * user_data,uint32_t channel,int status)777 static void dma_callback(const struct device *dev, void *user_data,
778 uint32_t channel, int status)
779 {
780 /* user_data directly holds the adc device */
781 struct adc_stm32_data *data = user_data;
782 const struct adc_stm32_cfg *config = data->dev->config;
783 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
784
785 LOG_DBG("dma callback");
786
787 if (channel == data->dma.channel) {
788 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
789 if (LL_ADC_IsActiveFlag_OVR(adc) || (status >= 0)) {
790 #else
791 if (status >= 0) {
792 #endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
793 data->samples_count = data->channel_count;
794 data->buffer += data->channel_count;
795 /* Stop the DMA engine, only to start it again when the callback returns
796 * ADC_ACTION_REPEAT or ADC_ACTION_CONTINUE, or the number of samples
797 * haven't been reached Starting the DMA engine is done
798 * within adc_context_start_sampling
799 */
800 dma_stop(data->dma.dma_dev, data->dma.channel);
801 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
802 LL_ADC_ClearFlag_OVR(adc);
803 #endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
804 /* No need to invalidate the cache because it's assumed that
805 * the address is in a non-cacheable SRAM region.
806 */
807 adc_context_on_sampling_done(&data->ctx, dev);
808 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE,
809 PM_ALL_SUBSTATES);
810 if (IS_ENABLED(CONFIG_PM_S2RAM)) {
811 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM,
812 PM_ALL_SUBSTATES);
813 }
814 } else if (status < 0) {
815 LOG_ERR("DMA sampling complete, but DMA reported error %d", status);
816 data->dma_error = status;
817 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
818 LL_ADC_REG_StopConversion(adc);
819 #endif
820 dma_stop(data->dma.dma_dev, data->dma.channel);
821 adc_context_complete(&data->ctx, status);
822 }
823 }
824 }
825 #endif /* CONFIG_ADC_STM32_DMA */
826
827 static uint8_t get_reg_value(const struct device *dev, uint32_t reg,
828 uint32_t shift, uint32_t mask)
829 {
830 const struct adc_stm32_cfg *config = dev->config;
831 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
832
833 uintptr_t addr = (uintptr_t)adc + reg;
834
835 return ((*(volatile uint32_t *)addr >> shift) & mask);
836 }
837
838 static void set_reg_value(const struct device *dev, uint32_t reg,
839 uint32_t shift, uint32_t mask, uint32_t value)
840 {
841 const struct adc_stm32_cfg *config = dev->config;
842 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
843
844 uintptr_t addr = (uintptr_t)adc + reg;
845
846 MODIFY_REG(*(volatile uint32_t *)addr, (mask << shift), (value << shift));
847 }
848
849 static int set_resolution(const struct device *dev,
850 const struct adc_sequence *sequence)
851 {
852 const struct adc_stm32_cfg *config = dev->config;
853 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
854 uint8_t res_reg_addr = 0xFF;
855 uint8_t res_shift = 0;
856 uint8_t res_mask = 0;
857 uint8_t res_reg_val = 0;
858 int i;
859
860 for (i = 0; i < config->res_table_size; i++) {
861 if (sequence->resolution == STM32_ADC_GET_REAL_VAL(config->res_table[i])) {
862 res_reg_addr = STM32_ADC_GET_REG(config->res_table[i]);
863 res_shift = STM32_ADC_GET_SHIFT(config->res_table[i]);
864 res_mask = STM32_ADC_GET_MASK(config->res_table[i]);
865 res_reg_val = STM32_ADC_GET_REG_VAL(config->res_table[i]);
866 break;
867 }
868 }
869
870 if (i == config->res_table_size) {
871 LOG_ERR("Invalid resolution");
872 return -EINVAL;
873 }
874
875 /*
876 * Some MCUs (like STM32F1x) have no register to configure resolution.
877 * These MCUs have a register address value of 0xFF and should be
878 * ignored.
879 */
880 if (res_reg_addr != 0xFF) {
881 /*
882 * We don't use LL_ADC_SetResolution and LL_ADC_GetResolution
883 * because they don't strictly use hardware resolution values
884 * and makes internal conversions for some series.
885 * (see stm32h7xx_ll_adc.h)
886 * Instead we set the register ourselves if needed.
887 */
888 if (get_reg_value(dev, res_reg_addr, res_shift, res_mask) != res_reg_val) {
889 /*
890 * Writing ADC_CFGR1 register while ADEN bit is set
891 * resets RES[1:0] bitfield. We need to disable and enable adc.
892 */
893 adc_stm32_disable(adc);
894 set_reg_value(dev, res_reg_addr, res_shift, res_mask, res_reg_val);
895 }
896 }
897
898 return 0;
899 }
900
901 static int set_sequencer(const struct device *dev)
902 {
903 const struct adc_stm32_cfg *config = dev->config;
904 struct adc_stm32_data *data = dev->data;
905 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
906
907 uint8_t channel_id;
908 uint8_t channel_index = 0;
909 uint32_t channels_mask = 0;
910
911 /* Iterate over selected channels in bitmask keeping track of:
912 * - channel_index: ranging from 0 -> ( data->channel_count - 1 )
913 * - channel_id: ordinal position of channel in data->channels bitmask
914 */
915 for (uint32_t channels = data->channels; channels;
916 channels &= ~BIT(channel_id), channel_index++) {
917 channel_id = find_lsb_set(channels) - 1;
918
919 uint32_t channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL(channel_id);
920
921 channels_mask |= channel;
922
923 #if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
924 if (config->sequencer_type == FULLY_CONFIGURABLE) {
925 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
926 /*
927 * Each channel in the sequence must be previously enabled in PCSEL.
928 * This register controls the analog switch integrated in the IO level.
929 */
930 LL_ADC_SetChannelPreselection(adc, channel);
931 #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32U5X */
932 LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel);
933 LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]);
934 }
935 #endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
936 }
937
938 #if ANY_ADC_SEQUENCER_TYPE_IS(NOT_FULLY_CONFIGURABLE)
939 if (config->sequencer_type == NOT_FULLY_CONFIGURABLE) {
940 LL_ADC_REG_SetSequencerChannels(adc, channels_mask);
941
942 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
943 !defined(CONFIG_SOC_SERIES_STM32L0X) && \
944 !defined(CONFIG_SOC_SERIES_STM32U5X) && \
945 !defined(CONFIG_SOC_SERIES_STM32WBAX)
946 /*
947 * After modifying sequencer it is mandatory to wait for the
948 * assertion of CCRDY flag
949 */
950 while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
951 }
952 LL_ADC_ClearFlag_CCRDY(adc);
953 #endif /* !CONFIG_SOC_SERIES_STM32F0X && !L0X && !U5X && !WBAX */
954 }
955 #endif /* ANY_ADC_SEQUENCER_TYPE_IS(NOT_FULLY_CONFIGURABLE) */
956
957 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \
958 DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
959 LL_ADC_SetSequencersScanMode(adc, LL_ADC_SEQ_SCAN_ENABLE);
960 #endif /* st_stm32f1_adc || st_stm32f4_adc */
961
962 return 0;
963 }
964
965 static int start_read(const struct device *dev,
966 const struct adc_sequence *sequence)
967 {
968 const struct adc_stm32_cfg *config = dev->config;
969 struct adc_stm32_data *data = dev->data;
970 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
971 int err;
972
973 data->buffer = sequence->buffer;
974 data->channels = sequence->channels;
975 data->channel_count = POPCOUNT(data->channels);
976 data->samples_count = 0;
977
978 if (data->channel_count == 0) {
979 LOG_ERR("No channels selected");
980 return -EINVAL;
981 }
982
983 #if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
984 if (data->channel_count > ARRAY_SIZE(table_seq_len)) {
985 LOG_ERR("Too many channels for sequencer. Max: %d", ARRAY_SIZE(table_seq_len));
986 return -EINVAL;
987 }
988 #endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
989
990 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && !defined(CONFIG_ADC_STM32_DMA)
991 /* Multiple samplings is only supported with DMA for F1 */
992 if (data->channel_count > 1) {
993 LOG_ERR("Without DMA, this device only supports single channel sampling");
994 return -EINVAL;
995 }
996 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && !CONFIG_ADC_STM32_DMA */
997
998 /* Check and set the resolution */
999 err = set_resolution(dev, sequence);
1000 if (err < 0) {
1001 return err;
1002 }
1003
1004 /* Configure the sequencer */
1005 err = set_sequencer(dev);
1006 if (err < 0) {
1007 return err;
1008 }
1009
1010 err = check_buffer(sequence, data->channel_count);
1011 if (err) {
1012 return err;
1013 }
1014
1015 #ifdef HAS_OVERSAMPLING
1016 err = adc_stm32_oversampling(adc, sequence->oversampling);
1017 if (err) {
1018 return err;
1019 }
1020 #else
1021 if (sequence->oversampling) {
1022 LOG_ERR("Oversampling not supported");
1023 return -ENOTSUP;
1024 }
1025 #endif /* HAS_OVERSAMPLING */
1026
1027 if (sequence->calibrate) {
1028 #if defined(HAS_CALIBRATION)
1029 adc_stm32_calibrate(dev);
1030 #else
1031 LOG_ERR("Calibration not supported");
1032 return -ENOTSUP;
1033 #endif
1034 }
1035
1036 /*
1037 * Make sure the ADC is enabled as it might have been disabled earlier
1038 * to set the resolution, to set the oversampling or to perform the
1039 * calibration.
1040 */
1041 adc_stm32_enable(adc);
1042
1043 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1044 LL_ADC_ClearFlag_OVR(adc);
1045 #endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
1046
1047 #if !defined(CONFIG_ADC_STM32_DMA)
1048 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
1049 /* Trigger an ISR after each sampling (not just end of sequence) */
1050 LL_ADC_REG_SetFlagEndOfConversion(adc, LL_ADC_REG_FLAG_EOC_UNITARY_CONV);
1051 LL_ADC_EnableIT_EOCS(adc);
1052 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1053 LL_ADC_EnableIT_EOS(adc);
1054 #else
1055 LL_ADC_EnableIT_EOC(adc);
1056 #endif
1057 #endif /* CONFIG_ADC_STM32_DMA */
1058
1059 /* This call will start the DMA */
1060 adc_context_start_read(&data->ctx, sequence);
1061
1062 int result = adc_context_wait_for_completion(&data->ctx);
1063
1064 #ifdef CONFIG_ADC_STM32_DMA
1065 /* check if there's anything wrong with dma start */
1066 result = (data->dma_error ? data->dma_error : result);
1067 #endif
1068
1069 return result;
1070 }
1071
1072 static void adc_context_start_sampling(struct adc_context *ctx)
1073 {
1074 struct adc_stm32_data *data =
1075 CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
1076 const struct device *dev = data->dev;
1077 const struct adc_stm32_cfg *config = dev->config;
1078 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
1079
1080 /* Remove warning for some series */
1081 ARG_UNUSED(adc);
1082
1083 data->repeat_buffer = data->buffer;
1084
1085 #ifdef CONFIG_ADC_STM32_DMA
1086 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
1087 /* Make sure DMA bit of ADC register CR2 is set to 0 before starting a DMA transfer */
1088 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE);
1089 #endif
1090 adc_stm32_dma_start(dev, data->buffer, data->channel_count);
1091 #endif
1092 adc_stm32_start_conversion(dev);
1093 }
1094
1095 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
1096 bool repeat_sampling)
1097 {
1098 struct adc_stm32_data *data =
1099 CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
1100
1101 if (repeat_sampling) {
1102 data->buffer = data->repeat_buffer;
1103 }
1104 }
1105
1106 #ifndef CONFIG_ADC_STM32_DMA
1107 static void adc_stm32_isr(const struct device *dev)
1108 {
1109 struct adc_stm32_data *data = dev->data;
1110 const struct adc_stm32_cfg *config =
1111 (const struct adc_stm32_cfg *)dev->config;
1112 ADC_TypeDef *adc = config->base;
1113
1114 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1115 if (LL_ADC_IsActiveFlag_EOS(adc) == 1) {
1116 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
1117 if (LL_ADC_IsActiveFlag_EOCS(adc) == 1) {
1118 #else
1119 if (LL_ADC_IsActiveFlag_EOC(adc) == 1) {
1120 #endif
1121 *data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
1122 /* ISR is triggered after each conversion, and at the end-of-sequence. */
1123 if (++data->samples_count == data->channel_count) {
1124 data->samples_count = 0;
1125 adc_context_on_sampling_done(&data->ctx, dev);
1126 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE,
1127 PM_ALL_SUBSTATES);
1128 if (IS_ENABLED(CONFIG_PM_S2RAM)) {
1129 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM,
1130 PM_ALL_SUBSTATES);
1131 }
1132 }
1133 }
1134
1135 LOG_DBG("%s ISR triggered.", dev->name);
1136 }
1137 #endif /* !CONFIG_ADC_STM32_DMA */
1138
1139 static void adc_context_on_complete(struct adc_context *ctx, int status)
1140 {
1141 struct adc_stm32_data *data =
1142 CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
1143 const struct adc_stm32_cfg *config = data->dev->config;
1144 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
1145
1146 ARG_UNUSED(status);
1147
1148 /* Reset acquisition time used for the sequence */
1149 data->acq_time_index[0] = -1;
1150 data->acq_time_index[1] = -1;
1151
1152 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
1153 /* Reset channel preselection register */
1154 LL_ADC_SetChannelPreselection(adc, 0);
1155 #else
1156 ARG_UNUSED(adc);
1157 #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32U5X */
1158 }
1159
1160 static int adc_stm32_read(const struct device *dev,
1161 const struct adc_sequence *sequence)
1162 {
1163 struct adc_stm32_data *data = dev->data;
1164 int error;
1165
1166 adc_context_lock(&data->ctx, false, NULL);
1167 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1168 if (IS_ENABLED(CONFIG_PM_S2RAM)) {
1169 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES);
1170 }
1171 error = start_read(dev, sequence);
1172 adc_context_release(&data->ctx, error);
1173
1174 return error;
1175 }
1176
1177 #ifdef CONFIG_ADC_ASYNC
1178 static int adc_stm32_read_async(const struct device *dev,
1179 const struct adc_sequence *sequence,
1180 struct k_poll_signal *async)
1181 {
1182 struct adc_stm32_data *data = dev->data;
1183 int error;
1184
1185 adc_context_lock(&data->ctx, true, async);
1186 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1187 if (IS_ENABLED(CONFIG_PM_S2RAM)) {
1188 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES);
1189 }
1190 error = start_read(dev, sequence);
1191 adc_context_release(&data->ctx, error);
1192
1193 return error;
1194 }
1195 #endif
1196
1197 static int adc_stm32_sampling_time_check(const struct device *dev, uint16_t acq_time)
1198 {
1199 const struct adc_stm32_cfg *config =
1200 (const struct adc_stm32_cfg *)dev->config;
1201
1202 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
1203 return 0;
1204 }
1205
1206 if (acq_time == ADC_ACQ_TIME_MAX) {
1207 return STM32_NB_SAMPLING_TIME - 1;
1208 }
1209
1210 for (int i = 0; i < STM32_NB_SAMPLING_TIME; i++) {
1211 if (acq_time == ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS,
1212 config->sampling_time_table[i])) {
1213 return i;
1214 }
1215 }
1216
1217 LOG_ERR("Sampling time value not supported.");
1218 return -EINVAL;
1219 }
1220
1221 static int adc_stm32_sampling_time_setup(const struct device *dev, uint8_t id,
1222 uint16_t acq_time)
1223 {
1224 const struct adc_stm32_cfg *config =
1225 (const struct adc_stm32_cfg *)dev->config;
1226 ADC_TypeDef *adc = config->base;
1227 struct adc_stm32_data *data = dev->data;
1228
1229 int acq_time_index;
1230
1231 acq_time_index = adc_stm32_sampling_time_check(dev, acq_time);
1232 if (acq_time_index < 0) {
1233 return acq_time_index;
1234 }
1235
1236 /*
1237 * For all series we use the fact that the macros LL_ADC_SAMPLINGTIME_*
1238 * that should be passed to the set functions are all coded on 3 bits
1239 * with 0 shift (ie 0 to 7). So acq_time_index is equivalent to the
1240 * macro we would use for the desired sampling time.
1241 */
1242 switch (config->num_sampling_time_common_channels) {
1243 case 0:
1244 #if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(0)
1245 ARG_UNUSED(data);
1246 LL_ADC_SetChannelSamplingTime(adc,
1247 __LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
1248 (uint32_t)acq_time_index);
1249 #endif
1250 break;
1251 case 1:
1252 #if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(1)
1253 /* Only one sampling time can be selected for all channels.
1254 * The first one we find is used, all others must match.
1255 */
1256 if ((data->acq_time_index[0] == -1) ||
1257 (acq_time_index == data->acq_time_index[0])) {
1258 /* Reg is empty or value matches */
1259 data->acq_time_index[0] = acq_time_index;
1260 LL_ADC_SetSamplingTimeCommonChannels(adc,
1261 (uint32_t)acq_time_index);
1262 } else {
1263 /* Reg is used and value does not match */
1264 LOG_ERR("Multiple sampling times not supported");
1265 return -EINVAL;
1266 }
1267 #endif
1268 break;
1269 case 2:
1270 #if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(2)
1271 /* Two different sampling times can be selected for all channels.
1272 * The first two we find are used, all others must match either one.
1273 */
1274 if ((data->acq_time_index[0] == -1) ||
1275 (acq_time_index == data->acq_time_index[0])) {
1276 /* 1st reg is empty or value matches 1st reg */
1277 data->acq_time_index[0] = acq_time_index;
1278 LL_ADC_SetChannelSamplingTime(adc,
1279 __LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
1280 LL_ADC_SAMPLINGTIME_COMMON_1);
1281 LL_ADC_SetSamplingTimeCommonChannels(adc,
1282 LL_ADC_SAMPLINGTIME_COMMON_1,
1283 (uint32_t)acq_time_index);
1284 } else if ((data->acq_time_index[1] == -1) ||
1285 (acq_time_index == data->acq_time_index[1])) {
1286 /* 2nd reg is empty or value matches 2nd reg */
1287 data->acq_time_index[1] = acq_time_index;
1288 LL_ADC_SetChannelSamplingTime(adc,
1289 __LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
1290 LL_ADC_SAMPLINGTIME_COMMON_2);
1291 LL_ADC_SetSamplingTimeCommonChannels(adc,
1292 LL_ADC_SAMPLINGTIME_COMMON_2,
1293 (uint32_t)acq_time_index);
1294 } else {
1295 /* Both regs are used, value does not match any of them */
1296 LOG_ERR("Only two different sampling times supported");
1297 return -EINVAL;
1298 }
1299 #endif
1300 break;
1301 default:
1302 LOG_ERR("Number of common sampling time channels not supported");
1303 return -EINVAL;
1304 }
1305 return 0;
1306 }
1307
1308 static int adc_stm32_channel_setup(const struct device *dev,
1309 const struct adc_channel_cfg *channel_cfg)
1310 {
1311 if (channel_cfg->differential) {
1312 LOG_ERR("Differential channels are not supported");
1313 return -EINVAL;
1314 }
1315
1316 if (channel_cfg->gain != ADC_GAIN_1) {
1317 LOG_ERR("Invalid channel gain");
1318 return -EINVAL;
1319 }
1320
1321 if (channel_cfg->reference != ADC_REF_INTERNAL) {
1322 LOG_ERR("Invalid channel reference");
1323 return -EINVAL;
1324 }
1325
1326 if (adc_stm32_sampling_time_setup(dev, channel_cfg->channel_id,
1327 channel_cfg->acquisition_time) != 0) {
1328 LOG_ERR("Invalid sampling time");
1329 return -EINVAL;
1330 }
1331
1332 LOG_DBG("Channel setup succeeded!");
1333
1334 return 0;
1335 }
1336
1337 /* This symbol takes the value 1 if one of the device instances */
1338 /* is configured in dts with a domain clock */
1339 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
1340 #define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1
1341 #else
1342 #define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0
1343 #endif
1344
1345 static int adc_stm32_set_clock(const struct device *dev)
1346 {
1347 const struct adc_stm32_cfg *config = dev->config;
1348 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
1349 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
1350
1351 ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
1352
1353 if (clock_control_on(clk,
1354 (clock_control_subsys_t) &config->pclken[0]) != 0) {
1355 return -EIO;
1356 }
1357
1358 if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
1359 /* Enable ADC clock source */
1360 if (clock_control_configure(clk,
1361 (clock_control_subsys_t) &config->pclken[1],
1362 NULL) != 0) {
1363 return -EIO;
1364 }
1365 }
1366
1367 #if defined(CONFIG_SOC_SERIES_STM32F0X)
1368 LL_ADC_SetClock(adc, config->clk_prescaler);
1369 #elif defined(CONFIG_SOC_SERIES_STM32C0X) || \
1370 defined(CONFIG_SOC_SERIES_STM32G0X) || \
1371 defined(CONFIG_SOC_SERIES_STM32L0X) || \
1372 (defined(CONFIG_SOC_SERIES_STM32WBX) && defined(ADC_SUPPORT_2_5_MSPS)) || \
1373 defined(CONFIG_SOC_SERIES_STM32WLX)
1374 if ((config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV1) ||
1375 (config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV2) ||
1376 (config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV4)) {
1377 LL_ADC_SetClock(adc, config->clk_prescaler);
1378 } else {
1379 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
1380 config->clk_prescaler);
1381 LL_ADC_SetClock(adc, LL_ADC_CLOCK_ASYNC);
1382 }
1383 #elif !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1384 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
1385 config->clk_prescaler);
1386 #endif
1387
1388 return 0;
1389 }
1390
1391 static int adc_stm32_init(const struct device *dev)
1392 {
1393 struct adc_stm32_data *data = dev->data;
1394 const struct adc_stm32_cfg *config = dev->config;
1395 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
1396 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
1397 int err;
1398
1399 ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
1400
1401 LOG_DBG("Initializing %s", dev->name);
1402
1403 if (!device_is_ready(clk)) {
1404 LOG_ERR("clock control device not ready");
1405 return -ENODEV;
1406 }
1407
1408 data->dev = dev;
1409
1410 /*
1411 * For series that use common channels for sampling time, all
1412 * conversion time for all channels on one ADC instance has to
1413 * be the same.
1414 * For series that use two common channels, there can be up to two
1415 * conversion times selected for all channels in a sequence.
1416 * This additional table is for checking that the conversion time
1417 * selection of all channels respects these requirements.
1418 */
1419 data->acq_time_index[0] = -1;
1420 data->acq_time_index[1] = -1;
1421
1422 adc_stm32_set_clock(dev);
1423
1424 /* Configure dt provided device signals when available */
1425 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1426 if (err < 0) {
1427 LOG_ERR("ADC pinctrl setup failed (%d)", err);
1428 return err;
1429 }
1430
1431 #if defined(CONFIG_SOC_SERIES_STM32U5X)
1432 /* Enable the independent analog supply */
1433 LL_PWR_EnableVDDA();
1434 #endif /* CONFIG_SOC_SERIES_STM32U5X */
1435
1436 #ifdef CONFIG_ADC_STM32_DMA
1437 if ((data->dma.dma_dev != NULL) &&
1438 !device_is_ready(data->dma.dma_dev)) {
1439 LOG_ERR("%s device not ready", data->dma.dma_dev->name);
1440 return -ENODEV;
1441 }
1442 #endif
1443
1444 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
1445 defined(CONFIG_SOC_SERIES_STM32L5X) || \
1446 defined(CONFIG_SOC_SERIES_STM32WBX) || \
1447 defined(CONFIG_SOC_SERIES_STM32G4X) || \
1448 defined(CONFIG_SOC_SERIES_STM32H5X) || \
1449 defined(CONFIG_SOC_SERIES_STM32H7X) || \
1450 defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
1451 defined(CONFIG_SOC_SERIES_STM32U5X)
1452 /*
1453 * L4, WB, G4, H5, H7 and U5 series STM32 needs to be awaken from deep sleep
1454 * mode, and restore its calibration parameters if there are some
1455 * previously stored calibration parameters.
1456 */
1457 LL_ADC_DisableDeepPowerDown(adc);
1458 #endif
1459
1460 /*
1461 * Many ADC modules need some time to be stabilized before performing
1462 * any enable or calibration actions.
1463 */
1464 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
1465 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
1466 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
1467 LL_ADC_EnableInternalRegulator(adc);
1468 /* Wait for Internal regulator stabilisation
1469 * Some series have a dedicated status bit, others relie on a delay
1470 */
1471 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(ADC_VER_V5_V90)
1472 /* ADC3 on H72x/H73x doesn't have the LDORDY status bit */
1473 if (adc == ADC3) {
1474 k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
1475 } else {
1476 while (LL_ADC_IsActiveFlag_LDORDY(adc) == 0) {
1477 }
1478 }
1479 #elif defined(CONFIG_SOC_SERIES_STM32H7X) || \
1480 defined(CONFIG_SOC_SERIES_STM32U5X) || \
1481 defined(CONFIG_SOC_SERIES_STM32WBAX)
1482 /* Don't use LL_ADC_IsActiveFlag_LDORDY since not present in U5 LL (1.5.0)
1483 * (internal issue 185106)
1484 */
1485 while ((READ_BIT(adc->ISR, LL_ADC_FLAG_LDORDY) != (LL_ADC_FLAG_LDORDY))) {
1486 }
1487 #else
1488 k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
1489 #endif
1490 #endif
1491
1492 if (config->irq_cfg_func) {
1493 config->irq_cfg_func();
1494 }
1495
1496 #if defined(HAS_CALIBRATION)
1497 adc_stm32_calibrate(dev);
1498 LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
1499 #endif /* HAS_CALIBRATION */
1500
1501 adc_context_unlock_unconditionally(&data->ctx);
1502
1503 return 0;
1504 }
1505
1506 #ifdef CONFIG_PM_DEVICE
1507 static int adc_stm32_suspend_setup(const struct device *dev)
1508 {
1509 const struct adc_stm32_cfg *config = dev->config;
1510 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
1511 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
1512 int err;
1513
1514 /* Disable ADC */
1515 adc_stm32_disable(adc);
1516
1517 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
1518 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
1519 !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
1520 /* Disable ADC internal voltage regulator */
1521 LL_ADC_DisableInternalRegulator(adc);
1522 while (LL_ADC_IsInternalRegulatorEnabled(adc) == 1U) {
1523 }
1524 #endif
1525
1526 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
1527 defined(CONFIG_SOC_SERIES_STM32L5X) || \
1528 defined(CONFIG_SOC_SERIES_STM32WBX) || \
1529 defined(CONFIG_SOC_SERIES_STM32G4X) || \
1530 defined(CONFIG_SOC_SERIES_STM32H5X) || \
1531 defined(CONFIG_SOC_SERIES_STM32H7X) || \
1532 defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
1533 defined(CONFIG_SOC_SERIES_STM32U5X)
1534 /*
1535 * L4, WB, G4, H5, H7 and U5 series STM32 needs to be put into
1536 * deep sleep mode.
1537 */
1538
1539 LL_ADC_EnableDeepPowerDown(adc);
1540 #endif
1541
1542 #if defined(CONFIG_SOC_SERIES_STM32U5X)
1543 /* Disable the independent analog supply */
1544 LL_PWR_DisableVDDA();
1545 #endif /* CONFIG_SOC_SERIES_STM32U5X */
1546
1547 /* Stop device clock. Note: fixed clocks are not handled yet. */
1548 err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken[0]);
1549 if (err != 0) {
1550 LOG_ERR("Could not disable ADC clock");
1551 return err;
1552 }
1553
1554 /* Move pins to sleep state */
1555 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
1556 if ((err < 0) && (err != -ENOENT)) {
1557 /*
1558 * If returning -ENOENT, no pins where defined for sleep mode :
1559 * Do not output on console (might sleep already) when going to sleep,
1560 * "ADC pinctrl sleep state not available"
1561 * and don't block PM suspend.
1562 * Else return the error.
1563 */
1564 return err;
1565 }
1566
1567 return 0;
1568 }
1569
1570 static int adc_stm32_pm_action(const struct device *dev,
1571 enum pm_device_action action)
1572 {
1573 switch (action) {
1574 case PM_DEVICE_ACTION_RESUME:
1575 return adc_stm32_init(dev);
1576 case PM_DEVICE_ACTION_SUSPEND:
1577 return adc_stm32_suspend_setup(dev);
1578 default:
1579 return -ENOTSUP;
1580 }
1581
1582 return 0;
1583 }
1584 #endif /* CONFIG_PM_DEVICE */
1585
1586 static const struct adc_driver_api api_stm32_driver_api = {
1587 .channel_setup = adc_stm32_channel_setup,
1588 .read = adc_stm32_read,
1589 #ifdef CONFIG_ADC_ASYNC
1590 .read_async = adc_stm32_read_async,
1591 #endif
1592 .ref_internal = STM32_ADC_VREF_MV, /* VREF is usually connected to VDD */
1593 };
1594
1595 #if defined(CONFIG_SOC_SERIES_STM32F0X)
1596 /* LL_ADC_CLOCK_ASYNC_DIV1 doesn't exist in F0 LL. Define it here. */
1597 #define LL_ADC_CLOCK_ASYNC_DIV1 LL_ADC_CLOCK_ASYNC
1598 #endif
1599
1600 /* st_prescaler property requires 2 elements : clock ASYNC/SYNC and DIV */
1601 #define ADC_STM32_CLOCK(x) DT_INST_PROP(x, st_adc_clock_source)
1602 #define ADC_STM32_DIV(x) DT_INST_PROP(x, st_adc_prescaler)
1603
1604 /* Macro to set the prefix depending on the 1st element: check if it is SYNC or ASYNC */
1605 #define ADC_STM32_CLOCK_PREFIX(x) \
1606 COND_CODE_1(IS_EQ(ADC_STM32_CLOCK(x), SYNC), \
1607 (LL_ADC_CLOCK_SYNC_PCLK_DIV), \
1608 (LL_ADC_CLOCK_ASYNC_DIV))
1609
1610 /* Concat prefix (1st element) and DIV value (2nd element) of st,adc-prescaler */
1611 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1612 #define ADC_STM32_DT_PRESC(x) 0
1613 #else
1614 #define ADC_STM32_DT_PRESC(x) \
1615 _CONCAT(ADC_STM32_CLOCK_PREFIX(x), ADC_STM32_DIV(x))
1616 #endif
1617
1618 #if defined(CONFIG_ADC_STM32_DMA)
1619
1620 #define ADC_DMA_CHANNEL_INIT(index, src_dev, dest_dev) \
1621 .dma = { \
1622 .dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(index, 0)), \
1623 .channel = DT_INST_DMAS_CELL_BY_IDX(index, 0, channel), \
1624 .dma_cfg = { \
1625 .dma_slot = STM32_DMA_SLOT_BY_IDX(index, 0, slot), \
1626 .channel_direction = STM32_DMA_CONFIG_DIRECTION( \
1627 STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)), \
1628 .source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE( \
1629 STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)), \
1630 .dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE( \
1631 STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)), \
1632 .source_burst_length = 1, /* SINGLE transfer */ \
1633 .dest_burst_length = 1, /* SINGLE transfer */ \
1634 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
1635 STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)), \
1636 .dma_callback = dma_callback, \
1637 .block_count = 2, \
1638 }, \
1639 .src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \
1640 STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)), \
1641 .dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \
1642 STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)), \
1643 }
1644
1645 #define ADC_STM32_IRQ_FUNC(index) \
1646 .irq_cfg_func = NULL,
1647
1648 #else /* CONFIG_ADC_STM32_DMA */
1649
1650 /*
1651 * For series that share interrupt lines for multiple ADC instances
1652 * and have separate interrupt lines for other ADCs (example,
1653 * STM32G473 has 5 ADC instances, ADC1 and ADC2 share IRQn 18 while
1654 * ADC3, ADC4 and ADC5 use IRQns 47, 61 and 62 respectively), generate
1655 * a single common ISR function for each IRQn and call adc_stm32_isr
1656 * for each device using that interrupt line for all enabled ADCs.
1657 *
1658 * To achieve the above, a "first" ADC instance must be chosen for all
1659 * ADC instances sharing the same IRQn. This "first" ADC instance
1660 * generates the code for the common ISR and for installing and
1661 * enabling it while any other ADC sharing the same IRQn skips this
1662 * code generation and does nothing. The common ISR code is generated
1663 * to include calls to adc_stm32_isr for all instances using that same
1664 * IRQn. From the example above, four ISR functions would be generated
1665 * for IRQn 18, 47, 61 and 62, with possible "first" ADC instances
1666 * being ADC1, ADC3, ADC4 and ADC5 if all ADCs were enabled, with the
1667 * ISR function 18 calling adc_stm32_isr for both ADC1 and ADC2.
1668 *
1669 * For some of the macros below, pseudo-code is provided to describe
1670 * its function.
1671 */
1672
1673 /*
1674 * return (irqn == device_irqn(index)) ? index : NULL
1675 */
1676 #define FIRST_WITH_IRQN_INTERNAL(index, irqn) \
1677 COND_CODE_1(IS_EQ(irqn, DT_INST_IRQN(index)), (index,), (EMPTY,))
1678
1679 /*
1680 * Returns the "first" instance's index:
1681 *
1682 * instances = []
1683 * for instance in all_active_adcs:
1684 * instances.append(first_with_irqn_internal(device_irqn(index)))
1685 * for instance in instances:
1686 * if instance == NULL:
1687 * instances.remove(instance)
1688 * return instances[0]
1689 */
1690 #define FIRST_WITH_IRQN(index) \
1691 GET_ARG_N(1, LIST_DROP_EMPTY(DT_INST_FOREACH_STATUS_OKAY_VARGS(FIRST_WITH_IRQN_INTERNAL, \
1692 DT_INST_IRQN(index))))
1693
1694 /*
1695 * Provides code for calling adc_stm32_isr for an instance if its IRQn
1696 * matches:
1697 *
1698 * if (irqn == device_irqn(index)):
1699 * return "adc_stm32_isr(DEVICE_DT_INST_GET(index));"
1700 */
1701 #define HANDLE_IRQS(index, irqn) \
1702 COND_CODE_1(IS_EQ(irqn, DT_INST_IRQN(index)), (adc_stm32_isr(DEVICE_DT_INST_GET(index));), \
1703 (EMPTY))
1704
1705 /*
1706 * Name of the common ISR for a given IRQn (taken from a device with a
1707 * given index). Example, for an ADC instance with IRQn 18, returns
1708 * "adc_stm32_isr_18".
1709 */
1710 #define ISR_FUNC(index) UTIL_CAT(adc_stm32_isr_, DT_INST_IRQN(index))
1711
1712 /*
1713 * Macro for generating code for the common ISRs (by looping of all
1714 * ADC instances that share the same IRQn as that of the given device
1715 * by index) and the function for setting up the ISR.
1716 *
1717 * Here is where both "first" and non-"first" instances have code
1718 * generated for their interrupts via HANDLE_IRQS.
1719 */
1720 #define GENERATE_ISR_CODE(index) \
1721 static void ISR_FUNC(index)(void) \
1722 { \
1723 DT_INST_FOREACH_STATUS_OKAY_VARGS(HANDLE_IRQS, DT_INST_IRQN(index)) \
1724 } \
1725 \
1726 static void UTIL_CAT(ISR_FUNC(index), _init)(void) \
1727 { \
1728 IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), ISR_FUNC(index), \
1729 NULL, 0); \
1730 irq_enable(DT_INST_IRQN(index)); \
1731 }
1732
1733 /*
1734 * Limit generating code to only the "first" instance:
1735 *
1736 * if (first_with_irqn(index) == index):
1737 * generate_isr_code(index)
1738 */
1739 #define GENERATE_ISR(index) \
1740 COND_CODE_1(IS_EQ(index, FIRST_WITH_IRQN(index)), (GENERATE_ISR_CODE(index)), (EMPTY))
1741
1742 DT_INST_FOREACH_STATUS_OKAY(GENERATE_ISR)
1743
1744 /* Only "first" instances need to call the ISR setup function */
1745 #define ADC_STM32_IRQ_FUNC(index) \
1746 .irq_cfg_func = COND_CODE_1(IS_EQ(index, FIRST_WITH_IRQN(index)), \
1747 (UTIL_CAT(ISR_FUNC(index), _init)), (NULL)),
1748
1749 #define ADC_DMA_CHANNEL_INIT(index, src_dev, dest_dev)
1750
1751 #endif /* CONFIG_ADC_STM32_DMA */
1752
1753 #define ADC_DMA_CHANNEL(id, src, dest) \
1754 COND_CODE_1(DT_INST_DMAS_HAS_IDX(id, 0), \
1755 (ADC_DMA_CHANNEL_INIT(id, src, dest)), \
1756 (/* Required for other adc instances without dma */))
1757
1758 #define ADC_STM32_INIT(index) \
1759 \
1760 PINCTRL_DT_INST_DEFINE(index); \
1761 \
1762 static const struct stm32_pclken pclken_##index[] = \
1763 STM32_DT_INST_CLOCKS(index); \
1764 \
1765 static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
1766 .base = (ADC_TypeDef *)DT_INST_REG_ADDR(index), \
1767 ADC_STM32_IRQ_FUNC(index) \
1768 .pclken = pclken_##index, \
1769 .pclk_len = DT_INST_NUM_CLOCKS(index), \
1770 .clk_prescaler = ADC_STM32_DT_PRESC(index), \
1771 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
1772 .sequencer_type = DT_INST_PROP(index, st_adc_sequencer), \
1773 .sampling_time_table = DT_INST_PROP(index, sampling_times), \
1774 .num_sampling_time_common_channels = \
1775 DT_INST_PROP_OR(index, num_sampling_time_common_channels, 0),\
1776 .res_table_size = DT_INST_PROP_LEN(index, resolutions), \
1777 .res_table = DT_INST_PROP(index, resolutions), \
1778 }; \
1779 \
1780 static struct adc_stm32_data adc_stm32_data_##index = { \
1781 ADC_CONTEXT_INIT_TIMER(adc_stm32_data_##index, ctx), \
1782 ADC_CONTEXT_INIT_LOCK(adc_stm32_data_##index, ctx), \
1783 ADC_CONTEXT_INIT_SYNC(adc_stm32_data_##index, ctx), \
1784 ADC_DMA_CHANNEL(index, PERIPHERAL, MEMORY) \
1785 }; \
1786 \
1787 PM_DEVICE_DT_INST_DEFINE(index, adc_stm32_pm_action); \
1788 \
1789 DEVICE_DT_INST_DEFINE(index, \
1790 &adc_stm32_init, PM_DEVICE_DT_INST_GET(index), \
1791 &adc_stm32_data_##index, &adc_stm32_cfg_##index, \
1792 POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
1793 &api_stm32_driver_api);
1794
1795 DT_INST_FOREACH_STATUS_OKAY(ADC_STM32_INIT)
1796
