1 /*
2 * Copyright (c) 2022, Basalte bv
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT atmel_sam_adc
8
9 #include <soc.h>
10 #include <zephyr/drivers/adc.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
13
14 #define ADC_CONTEXT_USES_KERNEL_TIMER
15 #include "adc_context.h"
16
17 #include <zephyr/logging/log.h>
18 #include <zephyr/irq.h>
19 LOG_MODULE_REGISTER(adc_sam, CONFIG_ADC_LOG_LEVEL);
20
21 #define SAM_ADC_NUM_CHANNELS 16
22 #define SAM_ADC_TEMP_CHANNEL 15
23
24 struct adc_sam_config {
25 Adc *regs;
26 const struct atmel_sam_pmc_config clock_cfg;
27
28 uint8_t prescaler;
29 uint8_t startup_time;
30 uint8_t settling_time;
31 uint8_t tracking_time;
32
33 const struct pinctrl_dev_config *pcfg;
34 void (*config_func)(const struct device *dev);
35 };
36
37 struct adc_sam_data {
38 struct adc_context ctx;
39 const struct device *dev;
40
41 /* Pointer to the buffer in the sequence. */
42 uint16_t *buffer;
43
44 /* Pointer to the beginning of a sample. Consider the number of
45 * channels in the sequence: this buffer changes by that amount
46 * so all the channels would get repeated.
47 */
48 uint16_t *repeat_buffer;
49
50 /* Number of active channels to fill buffer */
51 uint8_t num_active_channels;
52 };
53
count_bits(uint32_t val)54 static uint8_t count_bits(uint32_t val)
55 {
56 uint8_t res = 0;
57
58 while (val) {
59 res += val & 1U;
60 val >>= 1;
61 }
62
63 return res;
64 }
65
adc_sam_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)66 static int adc_sam_channel_setup(const struct device *dev,
67 const struct adc_channel_cfg *channel_cfg)
68 {
69 const struct adc_sam_config *const cfg = dev->config;
70 Adc *const adc = cfg->regs;
71
72 uint8_t channel_id = channel_cfg->channel_id;
73
74 if (channel_cfg->differential) {
75 if (channel_id != (channel_cfg->input_positive / 2U)
76 || channel_id != (channel_cfg->input_negative / 2U)) {
77 LOG_ERR("Invalid ADC differential input for channel %u", channel_id);
78 return -EINVAL;
79 }
80 } else {
81 if (channel_id != channel_cfg->input_positive) {
82 LOG_ERR("Invalid ADC single-ended input for channel %u", channel_id);
83 return -EINVAL;
84 }
85 }
86
87 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
88 LOG_ERR("Invalid ADC channel acquisition time");
89 return -EINVAL;
90 }
91
92 if (channel_cfg->reference != ADC_REF_EXTERNAL0) {
93 LOG_ERR("Invalid ADC channel reference (%d)", channel_cfg->reference);
94 return -EINVAL;
95 }
96
97 /* Enable internal temperature sensor (channel 15 / single-ended) */
98 if (channel_cfg->channel_id == SAM_ADC_TEMP_CHANNEL) {
99 adc->ADC_ACR |= ADC_ACR_TSON;
100 }
101
102 /* Set channel mode, always on both inputs */
103 if (channel_cfg->differential) {
104 adc->ADC_COR |= (ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U);
105 } else {
106 adc->ADC_COR &= ~((ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U));
107 }
108
109 /* Reset current gain */
110 adc->ADC_CGR &= ~(ADC_CGR_GAIN0_Msk << (channel_id * 2U));
111
112 switch (channel_cfg->gain) {
113 case ADC_GAIN_1_2:
114 if (!channel_cfg->differential) {
115 LOG_ERR("ADC 1/2x gain only allowed for differential channel");
116 return -EINVAL;
117 }
118 /* NOP */
119 break;
120 case ADC_GAIN_1:
121 adc->ADC_CGR |= ADC_CGR_GAIN0(1) << (channel_id * 2U);
122 break;
123 case ADC_GAIN_2:
124 adc->ADC_CGR |= ADC_CGR_GAIN0(2) << (channel_id * 2U);
125 break;
126 case ADC_GAIN_4:
127 if (channel_cfg->differential) {
128 LOG_ERR("ADC 4x gain only allowed for single-ended channel");
129 return -EINVAL;
130 }
131 adc->ADC_CGR |= ADC_CGR_GAIN0(3) << (channel_id * 2U);
132 break;
133 default:
134 LOG_ERR("Invalid ADC channel gain (%d)", channel_cfg->gain);
135 return -EINVAL;
136 }
137
138 return 0;
139 }
140
adc_sam_start_conversion(const struct device * dev)141 static void adc_sam_start_conversion(const struct device *dev)
142 {
143 const struct adc_sam_config *const cfg = dev->config;
144 Adc *const adc = cfg->regs;
145
146 adc->ADC_CR = ADC_CR_START;
147 }
148
149 /**
150 * This is only called once at the beginning of all the conversions,
151 * all channels as a group.
152 */
adc_context_start_sampling(struct adc_context * ctx)153 static void adc_context_start_sampling(struct adc_context *ctx)
154 {
155 struct adc_sam_data *data = CONTAINER_OF(ctx, struct adc_sam_data, ctx);
156 const struct adc_sam_config *const cfg = data->dev->config;
157 Adc *const adc = cfg->regs;
158
159 data->num_active_channels = count_bits(ctx->sequence.channels);
160
161 /* Disable all */
162 adc->ADC_CHDR = 0xffff;
163
164 /* Enable selected */
165 adc->ADC_CHER = ctx->sequence.channels;
166
167 LOG_DBG("Starting conversion for %u channels", data->num_active_channels);
168
169 adc_sam_start_conversion(data->dev);
170 }
171
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat)172 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat)
173 {
174 struct adc_sam_data *data = CONTAINER_OF(ctx, struct adc_sam_data, ctx);
175
176 if (repeat) {
177 data->buffer = data->repeat_buffer;
178 }
179 }
180
check_buffer_size(const struct adc_sequence * sequence,uint8_t active_channels)181 static int check_buffer_size(const struct adc_sequence *sequence,
182 uint8_t active_channels)
183 {
184 size_t needed_buffer_size = active_channels * sizeof(uint16_t);
185
186 if (sequence->options) {
187 needed_buffer_size *= (1 + sequence->options->extra_samplings);
188 }
189
190 if (sequence->buffer_size < needed_buffer_size) {
191 LOG_ERR("Provided buffer is too small (%u/%u)",
192 sequence->buffer_size, needed_buffer_size);
193 return -ENOMEM;
194 }
195
196 return 0;
197 }
198
start_read(const struct device * dev,const struct adc_sequence * sequence)199 static int start_read(const struct device *dev,
200 const struct adc_sequence *sequence)
201 {
202 struct adc_sam_data *data = dev->data;
203 uint32_t channels = sequence->channels;
204 int error;
205
206 /* Signal an error if the channel selection is invalid (no channels or
207 * a non-existing one is selected).
208 */
209 if (channels == 0U ||
210 (channels & (~0UL << SAM_ADC_NUM_CHANNELS))) {
211 LOG_ERR("Invalid selection of channels");
212 return -EINVAL;
213 }
214
215 if (sequence->oversampling != 0U) {
216 LOG_ERR("Oversampling is not supported");
217 return -EINVAL;
218 }
219
220 if (sequence->resolution != 12U) {
221 LOG_ERR("ADC resolution %d is not valid", sequence->resolution);
222 return -EINVAL;
223 }
224
225 data->num_active_channels = count_bits(channels);
226
227 error = check_buffer_size(sequence, data->num_active_channels);
228 if (error) {
229 return error;
230 }
231
232 data->buffer = sequence->buffer;
233 data->repeat_buffer = sequence->buffer;
234
235 /* At this point we allow the scheduler to do other things while
236 * we wait for the conversions to complete. This is provided by the
237 * adc_context functions. However, the caller of this function is
238 * blocked until the results are in.
239 */
240 adc_context_start_read(&data->ctx, sequence);
241
242 return adc_context_wait_for_completion(&data->ctx);
243 }
244
adc_sam_read(const struct device * dev,const struct adc_sequence * sequence)245 static int adc_sam_read(const struct device *dev,
246 const struct adc_sequence *sequence)
247 {
248 struct adc_sam_data *data = dev->data;
249 int error;
250
251 adc_context_lock(&data->ctx, false, NULL);
252 error = start_read(dev, sequence);
253 adc_context_release(&data->ctx, error);
254
255 return error;
256 }
257
adc_sam_isr(const struct device * dev)258 static void adc_sam_isr(const struct device *dev)
259 {
260 const struct adc_sam_config *const cfg = dev->config;
261 struct adc_sam_data *data = dev->data;
262 Adc *const adc = cfg->regs;
263
264 uint16_t result;
265
266 if (adc->ADC_ISR & ADC_ISR_DRDY) {
267 result = adc->ADC_LCDR & ADC_LCDR_LDATA_Msk;
268
269 *data->buffer++ = result;
270 data->num_active_channels--;
271
272 if (data->num_active_channels == 0) {
273 /* Called once all conversions have completed.*/
274 adc_context_on_sampling_done(&data->ctx, dev);
275 } else {
276 adc_sam_start_conversion(dev);
277 }
278 }
279 }
280
adc_sam_init(const struct device * dev)281 static int adc_sam_init(const struct device *dev)
282 {
283 const struct adc_sam_config *const cfg = dev->config;
284 struct adc_sam_data *data = dev->data;
285 Adc *const adc = cfg->regs;
286
287 int ret;
288 uint32_t frequency, conv_periods;
289
290 /* Get peripheral clock frequency */
291 ret = clock_control_get_rate(SAM_DT_PMC_CONTROLLER,
292 (clock_control_subsys_t)&cfg->clock_cfg,
293 &frequency);
294 if (ret < 0) {
295 LOG_ERR("Failed to get ADC peripheral clock rate (%d)", ret);
296 return -ENODEV;
297 }
298
299 /* Calculate ADC clock frequency */
300 frequency = frequency / 2U / (cfg->prescaler + 1U);
301 if (frequency < 1000000U || frequency > 22000000U) {
302 LOG_ERR("Invalid ADC clock frequency %d (1MHz < freq < 22Mhz)", frequency);
303 return -EINVAL;
304 }
305
306 /* The number of ADC pulses for conversion */
307 conv_periods = MAX(20U, cfg->tracking_time + 6U);
308
309 /* Calculate the sampling frequency */
310 frequency /= conv_periods;
311
312 /* Reset ADC controller */
313 adc->ADC_CR = ADC_CR_SWRST;
314
315 /* Reset Mode */
316 adc->ADC_MR = 0U;
317
318 /* Reset PDC transfer */
319 adc->ADC_PTCR = ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS;
320 adc->ADC_RCR = 0U;
321 adc->ADC_RNCR = 0U;
322
323 /* Set prescaler, timings and allow different analog settings for each channel */
324 adc->ADC_MR = ADC_MR_PRESCAL(cfg->prescaler)
325 | ADC_MR_STARTUP(cfg->startup_time)
326 | ADC_MR_SETTLING(cfg->settling_time)
327 | ADC_MR_TRACKTIM(cfg->tracking_time)
328 | ADC_MR_TRANSFER(2U) /* Should be 2 to guarantee the optimal hold time. */
329 | ADC_MR_ANACH_ALLOWED;
330
331 /**
332 * Set bias current control
333 * IBCTL = 00 is the required value for a sampling frequency below 500 kHz,
334 * and IBCTL = 01 for a sampling frequency between 500 kHz and 1 MHz.
335 */
336 adc->ADC_ACR = ADC_ACR_IBCTL(frequency < 500000U ? 0U : 1U);
337
338 /* Enable ADC clock in PMC */
339 ret = clock_control_on(SAM_DT_PMC_CONTROLLER,
340 (clock_control_subsys_t)&cfg->clock_cfg);
341 if (ret < 0) {
342 LOG_ERR("Failed to enable ADC clock (%d)", ret);
343 return -ENODEV;
344 }
345
346 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
347 if (ret < 0) {
348 return ret;
349 }
350
351 cfg->config_func(dev);
352
353 /* Enable data ready interrupt */
354 adc->ADC_IER = ADC_IER_DRDY;
355
356 data->dev = dev;
357
358 adc_context_unlock_unconditionally(&data->ctx);
359
360 return 0;
361 }
362
363 #ifdef CONFIG_ADC_ASYNC
adc_sam_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)364 static int adc_sam_read_async(const struct device *dev,
365 const struct adc_sequence *sequence,
366 struct k_poll_signal *async)
367 {
368 struct adc_sam_data *data = dev->data;
369 int error;
370
371 adc_context_lock(&data->ctx, true, async);
372 error = start_read(dev, sequence);
373 adc_context_release(&data->ctx, error);
374
375 return error;
376 }
377 #endif
378
379 static const struct adc_driver_api adc_sam_api = {
380 .channel_setup = adc_sam_channel_setup,
381 .read = adc_sam_read,
382 #ifdef CONFIG_ADC_ASYNC
383 .read_async = adc_sam_read_async,
384 #endif
385 };
386
387 #define ADC_SAM_DEVICE(n) \
388 PINCTRL_DT_INST_DEFINE(n); \
389 static void adc_sam_irq_config_##n(const struct device *dev) \
390 { \
391 IRQ_CONNECT(DT_INST_IRQN(n), \
392 DT_INST_IRQ(n, priority), \
393 adc_sam_isr, \
394 DEVICE_DT_INST_GET(n), 0); \
395 irq_enable(DT_INST_IRQN(n)); \
396 } \
397 static const struct adc_sam_config adc_sam_config_##n = { \
398 .regs = (Adc *)DT_INST_REG_ADDR(n), \
399 .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
400 .prescaler = DT_INST_PROP(n, prescaler), \
401 .startup_time = DT_INST_ENUM_IDX(n, startup_time), \
402 .settling_time = DT_INST_ENUM_IDX(n, settling_time), \
403 .tracking_time = DT_INST_ENUM_IDX(n, tracking_time), \
404 .config_func = &adc_sam_irq_config_##n, \
405 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
406 }; \
407 static struct adc_sam_data adc_sam_data_##n = { \
408 ADC_CONTEXT_INIT_TIMER(adc_sam_data_##n, ctx), \
409 ADC_CONTEXT_INIT_LOCK(adc_sam_data_##n, ctx), \
410 ADC_CONTEXT_INIT_SYNC(adc_sam_data_##n, ctx), \
411 .dev = DEVICE_DT_INST_GET(n), \
412 }; \
413 DEVICE_DT_INST_DEFINE(n, adc_sam_init, NULL, \
414 &adc_sam_data_##n, \
415 &adc_sam_config_##n, POST_KERNEL, \
416 CONFIG_ADC_INIT_PRIORITY, \
417 &adc_sam_api);
418
419 DT_INST_FOREACH_STATUS_OKAY(ADC_SAM_DEVICE)
420
