1 /*
2 * Copyright (c) 2021, STRIM LLC
3 *
4 * Based on adc_mcux_adc12.c, which are:
5 * Copyright (c) 2017-2018, NXP
6 * Copyright (c) 2019 Vestas Wind Systems A/S
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11 #define DT_DRV_COMPAT nxp_mcux_12b1msps_sar
12
13 #include <zephyr/drivers/adc.h>
14 #include <fsl_adc.h>
15 #include <zephyr/drivers/pinctrl.h>
16
17 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
18 #include <zephyr/logging/log.h>
19 #include <zephyr/irq.h>
20 LOG_MODULE_REGISTER(adc_mcux_12b1msps_sar);
21
22 #define ADC_CONTEXT_USES_KERNEL_TIMER
23 #include "adc_context.h"
24
25 struct mcux_12b1msps_sar_adc_config {
26 ADC_Type *base;
27 adc_clock_source_t clock_src;
28 adc_clock_driver_t clock_drv;
29 adc_reference_voltage_source_t ref_src;
30 adc_sample_period_mode_t sample_period_mode;
31 void (*irq_config_func)(const struct device *dev);
32 const struct pinctrl_dev_config *pincfg;
33 };
34
35 struct mcux_12b1msps_sar_adc_data {
36 const struct device *dev;
37 struct adc_context ctx;
38 uint16_t *buffer;
39 uint16_t *repeat_buffer;
40 uint32_t channels;
41 uint8_t channel_id;
42 };
43
mcux_12b1msps_sar_adc_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)44 static int mcux_12b1msps_sar_adc_channel_setup(const struct device *dev,
45 const struct adc_channel_cfg *channel_cfg)
46 {
47 uint8_t channel_id = channel_cfg->channel_id;
48
49 if (channel_id > (ADC_HC_ADCH_MASK >> ADC_HC_ADCH_SHIFT)) {
50 LOG_ERR("Invalid channel %d", channel_id);
51 return -EINVAL;
52 }
53
54 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
55 LOG_ERR("Unsupported channel acquisition time");
56 return -ENOTSUP;
57 }
58
59 if (channel_cfg->differential) {
60 LOG_ERR("Differential channels are not supported");
61 return -ENOTSUP;
62 }
63
64 if (channel_cfg->gain != ADC_GAIN_1) {
65 LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
66 return -ENOTSUP;
67 }
68
69 if (channel_cfg->reference != ADC_REF_INTERNAL) {
70 LOG_ERR("Unsupported channel reference");
71 return -ENOTSUP;
72 }
73
74 return 0;
75 }
76
mcux_12b1msps_sar_adc_start_read(const struct device * dev,const struct adc_sequence * sequence)77 static int mcux_12b1msps_sar_adc_start_read(const struct device *dev,
78 const struct adc_sequence *sequence)
79 {
80 const struct mcux_12b1msps_sar_adc_config *config = dev->config;
81 struct mcux_12b1msps_sar_adc_data *data = dev->data;
82 adc_hardware_average_mode_t mode;
83 adc_resolution_t resolution;
84 ADC_Type *base = config->base;
85 int error;
86 uint32_t tmp32;
87
88 switch (sequence->resolution) {
89 case 8:
90 resolution = kADC_Resolution8Bit;
91 break;
92 case 10:
93 resolution = kADC_Resolution10Bit;
94 break;
95 case 12:
96 resolution = kADC_Resolution12Bit;
97 break;
98 default:
99 LOG_ERR("Unsupported resolution %d", sequence->resolution);
100 return -ENOTSUP;
101 }
102
103 tmp32 = base->CFG & ~(ADC_CFG_MODE_MASK);
104 tmp32 |= ADC_CFG_MODE(resolution);
105 base->CFG = tmp32;
106
107 switch (sequence->oversampling) {
108 case 0:
109 mode = kADC_HardwareAverageDiasable;
110 break;
111 case 2:
112 mode = kADC_HardwareAverageCount4;
113 break;
114 case 3:
115 mode = kADC_HardwareAverageCount8;
116 break;
117 case 4:
118 mode = kADC_HardwareAverageCount16;
119 break;
120 case 5:
121 mode = kADC_HardwareAverageCount32;
122 break;
123 default:
124 LOG_ERR("Unsupported oversampling value %d",
125 sequence->oversampling);
126 return -ENOTSUP;
127 }
128 ADC_SetHardwareAverageConfig(config->base, mode);
129
130 data->buffer = sequence->buffer;
131 adc_context_start_read(&data->ctx, sequence);
132 error = adc_context_wait_for_completion(&data->ctx);
133
134 return error;
135 }
136
mcux_12b1msps_sar_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)137 static int mcux_12b1msps_sar_adc_read_async(const struct device *dev,
138 const struct adc_sequence *sequence,
139 struct k_poll_signal *async)
140 {
141 struct mcux_12b1msps_sar_adc_data *data = dev->data;
142 int error;
143
144 adc_context_lock(&data->ctx, async ? true : false, async);
145 error = mcux_12b1msps_sar_adc_start_read(dev, sequence);
146 adc_context_release(&data->ctx, error);
147
148 return error;
149 }
150
mcux_12b1msps_sar_adc_read(const struct device * dev,const struct adc_sequence * sequence)151 static int mcux_12b1msps_sar_adc_read(const struct device *dev,
152 const struct adc_sequence *sequence)
153 {
154 return mcux_12b1msps_sar_adc_read_async(dev, sequence, NULL);
155 }
156
mcux_12b1msps_sar_adc_start_channel(const struct device * dev)157 static void mcux_12b1msps_sar_adc_start_channel(const struct device *dev)
158 {
159 const struct mcux_12b1msps_sar_adc_config *config = dev->config;
160 struct mcux_12b1msps_sar_adc_data *data = dev->data;
161
162 adc_channel_config_t channel_config;
163 uint32_t channel_group = 0U;
164
165 data->channel_id = find_lsb_set(data->channels) - 1;
166
167 LOG_DBG("Starting channel %d", data->channel_id);
168 channel_config.enableInterruptOnConversionCompleted = true;
169 channel_config.channelNumber = data->channel_id;
170 ADC_SetChannelConfig(config->base, channel_group, &channel_config);
171 }
172
adc_context_start_sampling(struct adc_context * ctx)173 static void adc_context_start_sampling(struct adc_context *ctx)
174 {
175 struct mcux_12b1msps_sar_adc_data *data =
176 CONTAINER_OF(ctx, struct mcux_12b1msps_sar_adc_data, ctx);
177
178 data->channels = ctx->sequence.channels;
179 data->repeat_buffer = data->buffer;
180
181 mcux_12b1msps_sar_adc_start_channel(data->dev);
182 }
183
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)184 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
185 bool repeat_sampling)
186 {
187 struct mcux_12b1msps_sar_adc_data *data =
188 CONTAINER_OF(ctx, struct mcux_12b1msps_sar_adc_data, ctx);
189
190 if (repeat_sampling) {
191 data->buffer = data->repeat_buffer;
192 }
193 }
194
mcux_12b1msps_sar_adc_isr(const struct device * dev)195 static void mcux_12b1msps_sar_adc_isr(const struct device *dev)
196 {
197 const struct mcux_12b1msps_sar_adc_config *config = dev->config;
198 struct mcux_12b1msps_sar_adc_data *data = dev->data;
199 ADC_Type *base = config->base;
200 uint32_t channel_group = 0U;
201 uint16_t result;
202
203 result = ADC_GetChannelConversionValue(base, channel_group);
204 LOG_DBG("Finished channel %d. Result is 0x%04x", data->channel_id,
205 result);
206
207 *data->buffer++ = result;
208 data->channels &= ~BIT(data->channel_id);
209
210 if (data->channels) {
211 mcux_12b1msps_sar_adc_start_channel(dev);
212 } else {
213 adc_context_on_sampling_done(&data->ctx, dev);
214 }
215 }
216
mcux_12b1msps_sar_adc_init(const struct device * dev)217 static int mcux_12b1msps_sar_adc_init(const struct device *dev)
218 {
219 const struct mcux_12b1msps_sar_adc_config *config = dev->config;
220 struct mcux_12b1msps_sar_adc_data *data = dev->data;
221 ADC_Type *base = config->base;
222 adc_config_t adc_config;
223 int err;
224
225 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
226 if (err) {
227 return err;
228 }
229
230 ADC_GetDefaultConfig(&adc_config);
231
232 adc_config.referenceVoltageSource = config->ref_src;
233 adc_config.clockSource = config->clock_src;
234 adc_config.clockDriver = config->clock_drv;
235 adc_config.samplePeriodMode = config->sample_period_mode;
236 adc_config.resolution = kADC_Resolution12Bit;
237 adc_config.enableContinuousConversion = false;
238 adc_config.enableOverWrite = false;
239 adc_config.enableHighSpeed = false;
240 adc_config.enableLowPower = false;
241 adc_config.enableLongSample = false;
242 adc_config.enableAsynchronousClockOutput = true;
243
244 ADC_Init(base, &adc_config);
245
246 #if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && \
247 FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
248 ADC_EnableHardwareTrigger(base, false);
249 #endif
250
251 if (kStatus_Success == ADC_DoAutoCalibration(base)) {
252 LOG_DBG("ADC_DoAutoCalibration() Done.");
253 } else {
254 LOG_WRN("ADC_DoAutoCalibration() Failed.");
255 }
256
257 config->irq_config_func(dev);
258 data->dev = dev;
259
260 adc_context_unlock_unconditionally(&data->ctx);
261
262 return 0;
263 }
264
265 static const struct adc_driver_api mcux_12b1msps_sar_adc_driver_api = {
266 .channel_setup = mcux_12b1msps_sar_adc_channel_setup,
267 .read = mcux_12b1msps_sar_adc_read,
268 #ifdef CONFIG_ADC_ASYNC
269 .read_async = mcux_12b1msps_sar_adc_read_async,
270 #endif
271 .ref_internal = 3300,
272 };
273
274 #define ASSERT_WITHIN_RANGE(val, min, max, str) \
275 BUILD_ASSERT(val >= min && val <= max, str)
276 #define ASSERT_RT_ADC_CLK_DIV_VALID(val, str) \
277 BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8, str)
278 #define TO_RT_ADC_CLOCK_DIV(val) _DO_CONCAT(kADC_ClockDriver, val)
279
280 #define ACD_MCUX_12B1MSPS_SAR_INIT(n) \
281 static void mcux_12b1msps_sar_adc_config_func_##n(const struct device *dev); \
282 \
283 ASSERT_RT_ADC_CLK_DIV_VALID(DT_INST_PROP(n, clk_divider), \
284 "Invalid clock divider"); \
285 ASSERT_WITHIN_RANGE(DT_INST_PROP(n, sample_period_mode), 0, 3, \
286 "Invalid sample period mode"); \
287 PINCTRL_DT_INST_DEFINE(n); \
288 \
289 static const struct mcux_12b1msps_sar_adc_config mcux_12b1msps_sar_adc_config_##n = { \
290 .base = (ADC_Type *)DT_INST_REG_ADDR(n), \
291 .clock_src = kADC_ClockSourceAD, \
292 .clock_drv = \
293 TO_RT_ADC_CLOCK_DIV(DT_INST_PROP(n, clk_divider)), \
294 .ref_src = kADC_ReferenceVoltageSourceAlt0, \
295 .sample_period_mode = DT_INST_PROP(n, sample_period_mode), \
296 .irq_config_func = mcux_12b1msps_sar_adc_config_func_##n, \
297 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
298 }; \
299 \
300 static struct mcux_12b1msps_sar_adc_data mcux_12b1msps_sar_adc_data_##n = { \
301 ADC_CONTEXT_INIT_TIMER(mcux_12b1msps_sar_adc_data_##n, ctx), \
302 ADC_CONTEXT_INIT_LOCK(mcux_12b1msps_sar_adc_data_##n, ctx), \
303 ADC_CONTEXT_INIT_SYNC(mcux_12b1msps_sar_adc_data_##n, ctx), \
304 }; \
305 \
306 DEVICE_DT_INST_DEFINE(n, &mcux_12b1msps_sar_adc_init, NULL, \
307 &mcux_12b1msps_sar_adc_data_##n, &mcux_12b1msps_sar_adc_config_##n, \
308 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
309 &mcux_12b1msps_sar_adc_driver_api); \
310 \
311 static void mcux_12b1msps_sar_adc_config_func_##n(const struct device *dev) \
312 { \
313 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
314 mcux_12b1msps_sar_adc_isr, DEVICE_DT_INST_GET(n), 0); \
315 \
316 irq_enable(DT_INST_IRQN(n)); \
317 }
318
319 DT_INST_FOREACH_STATUS_OKAY(ACD_MCUX_12B1MSPS_SAR_INIT)
320
