1 /*
2  * Copyright (c) 2023 SILA Embedded Solutions GmbH
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <zephyr/device.h>
7 #include <zephyr/devicetree.h>
8 #include <zephyr/drivers/adc.h>
9 #include <zephyr/drivers/spi.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/logging/log.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/sys/byteorder.h>
14 #include <zephyr/sys/util.h>
15 
16 #define ADC_CONTEXT_USES_KERNEL_TIMER 1
17 #include "adc_context.h"
18 
19 LOG_MODULE_REGISTER(max11102_17, CONFIG_ADC_LOG_LEVEL);
20 
21 struct max11102_17_config {
22 	struct spi_dt_spec bus;
23 	const struct gpio_dt_spec gpio_chsel;
24 	uint8_t resolution;
25 	uint8_t channel_count;
26 };
27 
28 struct max11102_17_data {
29 	struct adc_context ctx;
30 	struct k_sem acquire_signal;
31 	int16_t *buffer;
32 	int16_t *buffer_ptr;
33 	uint8_t current_channel_id;
34 	uint8_t sequence_channel_id;
35 #if CONFIG_ADC_ASYNC
36 	struct k_thread thread;
37 
38 	K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_MAX11102_17_ACQUISITION_THREAD_STACK_SIZE);
39 #endif /* CONFIG_ADC_ASYNC */
40 };
41 
max11102_17_switch_channel(const struct device * dev)42 static int max11102_17_switch_channel(const struct device *dev)
43 {
44 	const struct max11102_17_config *config = dev->config;
45 	struct max11102_17_data *data = dev->data;
46 	int result;
47 	uint8_t buffer_rx[1];
48 	const struct spi_buf rx_buf[] = {{
49 		.buf = buffer_rx,
50 		.len = ARRAY_SIZE(buffer_rx),
51 	}};
52 	const struct spi_buf_set rx = {
53 		.buffers = rx_buf,
54 		.count = ARRAY_SIZE(rx_buf),
55 	};
56 	struct spi_dt_spec bus;
57 
58 	memcpy(&bus, &config->bus, sizeof(bus));
59 	bus.config.operation |= SPI_HOLD_ON_CS;
60 
61 	result = spi_read_dt(&bus, &rx);
62 	if (result != 0) {
63 		LOG_ERR("read failed with error %i", result);
64 		return result;
65 	}
66 
67 	gpio_pin_set_dt(&config->gpio_chsel, data->current_channel_id);
68 
69 	result = spi_read_dt(&config->bus, &rx);
70 	if (result != 0) {
71 		LOG_ERR("read failed with error %i", result);
72 		return result;
73 	}
74 
75 	return 0;
76 }
77 
max11102_17_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)78 static int max11102_17_channel_setup(const struct device *dev,
79 				     const struct adc_channel_cfg *channel_cfg)
80 {
81 	const struct max11102_17_config *config = dev->config;
82 
83 	LOG_DBG("read from ADC channel %i", channel_cfg->channel_id);
84 
85 	if (channel_cfg->reference != ADC_REF_EXTERNAL0) {
86 		LOG_ERR("invalid reference %i", channel_cfg->reference);
87 		return -EINVAL;
88 	}
89 
90 	if (channel_cfg->gain != ADC_GAIN_1) {
91 		LOG_ERR("invalid gain %i", channel_cfg->gain);
92 		return -EINVAL;
93 	}
94 
95 	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
96 		LOG_ERR("invalid acquisition time %i", channel_cfg->acquisition_time);
97 		return -EINVAL;
98 	}
99 
100 	if (channel_cfg->differential != 0) {
101 		LOG_ERR("differential inputs are not supported");
102 		return -EINVAL;
103 	}
104 
105 	if (channel_cfg->channel_id > config->channel_count) {
106 		LOG_ERR("invalid channel selection %i", channel_cfg->channel_id);
107 		return -EINVAL;
108 	}
109 
110 	return 0;
111 }
112 
max11102_17_validate_buffer_size(const struct adc_sequence * sequence)113 static int max11102_17_validate_buffer_size(const struct adc_sequence *sequence)
114 {
115 	size_t necessary = sizeof(int16_t);
116 
117 	if (sequence->options) {
118 		necessary *= (1 + sequence->options->extra_samplings);
119 	}
120 
121 	if (sequence->buffer_size < necessary) {
122 		return -ENOMEM;
123 	}
124 
125 	return 0;
126 }
127 
max11102_17_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)128 static int max11102_17_validate_sequence(const struct device *dev,
129 					 const struct adc_sequence *sequence)
130 {
131 	const struct max11102_17_config *config = dev->config;
132 	struct max11102_17_data *data = dev->data;
133 	size_t sequence_channel_count = 0;
134 	const size_t channel_maximum = 8*sizeof(sequence->channels);
135 
136 	if (sequence->resolution != config->resolution) {
137 		LOG_ERR("invalid resolution");
138 		return -EINVAL;
139 	}
140 
141 	for (size_t i = 0; i < channel_maximum; ++i) {
142 		if ((BIT(i) & sequence->channels) == 0) {
143 			continue;
144 		}
145 
146 		if (i > config->channel_count) {
147 			LOG_ERR("invalid channel selection");
148 			return -EINVAL;
149 		}
150 
151 		sequence_channel_count++;
152 		data->sequence_channel_id = i;
153 	}
154 
155 	if (sequence_channel_count == 0) {
156 		LOG_ERR("no channel selected");
157 		return -EINVAL;
158 	}
159 
160 	if (sequence_channel_count > 1) {
161 		LOG_ERR("multiple channels selected");
162 		return -EINVAL;
163 	}
164 
165 	if (sequence->oversampling) {
166 		LOG_ERR("oversampling is not supported");
167 		return -EINVAL;
168 	}
169 
170 	return max11102_17_validate_buffer_size(sequence);
171 }
172 
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)173 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
174 {
175 	struct max11102_17_data *data = CONTAINER_OF(ctx, struct max11102_17_data, ctx);
176 
177 	if (repeat_sampling) {
178 		data->buffer = data->buffer_ptr;
179 	}
180 }
181 
adc_context_start_sampling(struct adc_context * ctx)182 static void adc_context_start_sampling(struct adc_context *ctx)
183 {
184 	struct max11102_17_data *data = CONTAINER_OF(ctx, struct max11102_17_data, ctx);
185 
186 	data->buffer_ptr = data->buffer;
187 	k_sem_give(&data->acquire_signal);
188 }
189 
max11102_17_adc_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)190 static int max11102_17_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
191 				      bool wait)
192 {
193 	int result;
194 	struct max11102_17_data *data = dev->data;
195 
196 	result = max11102_17_validate_sequence(dev, sequence);
197 
198 	if (result != 0) {
199 		LOG_ERR("sequence validation failed");
200 		return result;
201 	}
202 
203 	data->buffer = sequence->buffer;
204 
205 	adc_context_start_read(&data->ctx, sequence);
206 
207 	if (wait) {
208 		result = adc_context_wait_for_completion(&data->ctx);
209 	}
210 
211 	return result;
212 }
213 
max11102_17_read_sample(const struct device * dev,int16_t * sample)214 static int max11102_17_read_sample(const struct device *dev, int16_t *sample)
215 {
216 	const struct max11102_17_config *config = dev->config;
217 	int result;
218 	size_t trailing_bits = 15 - config->resolution;
219 	uint8_t buffer_rx[2];
220 	const struct spi_buf rx_buf[] = {{
221 		.buf = buffer_rx,
222 		.len = ARRAY_SIZE(buffer_rx),
223 	}};
224 	const struct spi_buf_set rx = {
225 		.buffers = rx_buf,
226 		.count = ARRAY_SIZE(rx_buf),
227 	};
228 
229 	result = spi_read_dt(&config->bus, &rx);
230 
231 	if (result != 0) {
232 		LOG_ERR("read failed with error %i", result);
233 		return result;
234 	}
235 
236 	*sample = sys_get_be16(buffer_rx);
237 	LOG_DBG("raw sample: 0x%04X", *sample);
238 
239 	*sample = *sample >> trailing_bits;
240 	*sample = *sample & GENMASK(config->resolution, 0);
241 	LOG_DBG("sample: 0x%04X", *sample);
242 
243 	return 0;
244 }
245 
max11102_17_adc_perform_read(const struct device * dev)246 static int max11102_17_adc_perform_read(const struct device *dev)
247 {
248 	int result;
249 	struct max11102_17_data *data = dev->data;
250 
251 	k_sem_take(&data->acquire_signal, K_FOREVER);
252 
253 	if (data->sequence_channel_id != data->current_channel_id) {
254 		LOG_DBG("switch channel selection");
255 		data->current_channel_id = data->sequence_channel_id;
256 		max11102_17_switch_channel(dev);
257 	}
258 
259 	result = max11102_17_read_sample(dev, data->buffer);
260 	if (result != 0) {
261 		LOG_ERR("reading sample failed");
262 		adc_context_complete(&data->ctx, result);
263 		return result;
264 	}
265 
266 	data->buffer++;
267 
268 	adc_context_on_sampling_done(&data->ctx, dev);
269 
270 	return result;
271 }
272 
273 #if CONFIG_ADC_ASYNC
max11102_17_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)274 static int max11102_17_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
275 				      struct k_poll_signal *async)
276 {
277 	int result;
278 	struct max11102_17_data *data = dev->data;
279 
280 	adc_context_lock(&data->ctx, true, async);
281 	result = max11102_17_adc_start_read(dev, sequence, true);
282 	adc_context_release(&data->ctx, result);
283 
284 	return result;
285 }
286 
max11102_17_read(const struct device * dev,const struct adc_sequence * sequence)287 static int max11102_17_read(const struct device *dev, const struct adc_sequence *sequence)
288 {
289 	int result;
290 	struct max11102_17_data *data = dev->data;
291 
292 	adc_context_lock(&data->ctx, false, NULL);
293 	result = max11102_17_adc_start_read(dev, sequence, true);
294 	adc_context_release(&data->ctx, result);
295 
296 	return result;
297 }
298 
299 #else
max11102_17_read(const struct device * dev,const struct adc_sequence * sequence)300 static int max11102_17_read(const struct device *dev, const struct adc_sequence *sequence)
301 {
302 	int result;
303 	struct max11102_17_data *data = dev->data;
304 
305 	adc_context_lock(&data->ctx, false, NULL);
306 	result = max11102_17_adc_start_read(dev, sequence, false);
307 
308 	while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
309 		result = max11102_17_adc_perform_read(dev);
310 	}
311 
312 	adc_context_release(&data->ctx, result);
313 	return result;
314 }
315 #endif
316 
317 #if CONFIG_ADC_ASYNC
max11102_17_acquisition_thread(void * p1,void * p2,void * p3)318 static void max11102_17_acquisition_thread(void *p1, void *p2, void *p3)
319 {
320 	ARG_UNUSED(p2);
321 	ARG_UNUSED(p3);
322 
323 	const struct device *dev = p1;
324 	while (true) {
325 		max11102_17_adc_perform_read(dev);
326 	}
327 }
328 #endif
329 
max11102_17_init(const struct device * dev)330 static int max11102_17_init(const struct device *dev)
331 {
332 	int result;
333 	const struct max11102_17_config *config = dev->config;
334 	struct max11102_17_data *data = dev->data;
335 	int16_t sample;
336 
337 	adc_context_init(&data->ctx);
338 
339 	k_sem_init(&data->acquire_signal, 0, 1);
340 
341 	if (!spi_is_ready_dt(&config->bus)) {
342 		LOG_ERR("SPI device is not ready");
343 		return -ENODEV;
344 	}
345 
346 	switch (config->channel_count) {
347 	case 1:
348 		if (config->gpio_chsel.port != NULL) {
349 			LOG_ERR("GPIO for chsel set with only one channel");
350 			return -EINVAL;
351 		}
352 		break;
353 	case 2:
354 		if (config->gpio_chsel.port == NULL) {
355 			LOG_ERR("no GPIO for chsel set with two channels");
356 			return -EINVAL;
357 		}
358 
359 		result = gpio_pin_configure_dt(&config->gpio_chsel, GPIO_OUTPUT_INACTIVE);
360 		if (result != 0) {
361 			LOG_ERR("failed to initialize GPIO for chsel");
362 			return result;
363 		}
364 		break;
365 	default:
366 		LOG_ERR("invalid number of channels (%i)", config->channel_count);
367 		return -EINVAL;
368 	}
369 
370 	data->current_channel_id = 0;
371 
372 #if CONFIG_ADC_ASYNC
373 	k_tid_t tid = k_thread_create(
374 		&data->thread, data->stack, CONFIG_ADC_MAX11102_17_ACQUISITION_THREAD_STACK_SIZE,
375 		max11102_17_acquisition_thread, (void *)dev, NULL, NULL,
376 		CONFIG_ADC_MAX11102_17_ACQUISITION_THREAD_INIT_PRIO, 0, K_NO_WAIT);
377 	k_thread_name_set(tid, "adc_max11102_17");
378 #endif
379 
380 	/* power up time is one conversion cycle */
381 	result = max11102_17_read_sample(dev, &sample);
382 	if (result != 0) {
383 		LOG_ERR("unable to read dummy sample for power up timing");
384 		return result;
385 	}
386 
387 	adc_context_unlock_unconditionally(&data->ctx);
388 
389 	return result;
390 }
391 
392 static const struct adc_driver_api api = {
393 	.channel_setup = max11102_17_channel_setup,
394 	.read = max11102_17_read,
395 	.ref_internal = 0,
396 #ifdef CONFIG_ADC_ASYNC
397 	.read_async = max11102_17_adc_read_async,
398 #endif
399 };
400 
401 BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
402 	     "CONFIG_ADC_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
403 
404 #define ADC_MAX11102_17_INST_DEFINE(index, name, res, channels)                                    \
405 	static const struct max11102_17_config config_##name##_##index = {                         \
406 		.bus = SPI_DT_SPEC_INST_GET(                                                       \
407 			index,                                                                     \
408 			SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8), 0),  \
409 		.gpio_chsel = GPIO_DT_SPEC_INST_GET_OR(index, chsel_gpios, {0}),                   \
410 		.resolution = res,                                                                 \
411 		.channel_count = channels,                                                         \
412 	};                                                                                         \
413 	static struct max11102_17_data data_##name##_##index;                                      \
414 	DEVICE_DT_INST_DEFINE(index, max11102_17_init, NULL, &data_##name##_##index,               \
415 			      &config_##name##_##index, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,     \
416 			      &api);
417 
418 #define DT_DRV_COMPAT           maxim_max11102
419 #define ADC_MAX11102_RESOLUTION 12
420 #define ADC_MAX11102_CHANNELS   2
421 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
422 				  ADC_MAX11102_RESOLUTION, ADC_MAX11102_CHANNELS)
423 #undef DT_DRV_COMPAT
424 
425 #define DT_DRV_COMPAT           maxim_max11103
426 #define ADC_MAX11103_RESOLUTION 12
427 #define ADC_MAX11103_CHANNELS   2
428 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
429 				  ADC_MAX11103_RESOLUTION, ADC_MAX11103_CHANNELS)
430 #undef DT_DRV_COMPAT
431 
432 #define DT_DRV_COMPAT           maxim_max11105
433 #define ADC_MAX11105_RESOLUTION 12
434 #define ADC_MAX11105_CHANNELS   1
435 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
436 				  ADC_MAX11105_RESOLUTION, ADC_MAX11105_CHANNELS)
437 #undef DT_DRV_COMPAT
438 
439 #define DT_DRV_COMPAT           maxim_max11106
440 #define ADC_MAX11106_RESOLUTION 10
441 #define ADC_MAX11106_CHANNELS   2
442 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
443 				  ADC_MAX11106_RESOLUTION, ADC_MAX11106_CHANNELS)
444 #undef DT_DRV_COMPAT
445 
446 #define DT_DRV_COMPAT           maxim_max11110
447 #define ADC_MAX11110_RESOLUTION 10
448 #define ADC_MAX11110_CHANNELS   1
449 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
450 				  ADC_MAX11110_RESOLUTION, ADC_MAX11110_CHANNELS)
451 #undef DT_DRV_COMPAT
452 
453 #define DT_DRV_COMPAT           maxim_max11111
454 #define ADC_MAX11111_RESOLUTION 8
455 #define ADC_MAX11111_CHANNELS   2
456 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
457 				  ADC_MAX11111_RESOLUTION, ADC_MAX11111_CHANNELS)
458 #undef DT_DRV_COMPAT
459 
460 #define DT_DRV_COMPAT           maxim_max11115
461 #define ADC_MAX11115_RESOLUTION 8
462 #define ADC_MAX11115_CHANNELS   1
463 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
464 				  ADC_MAX11115_RESOLUTION, ADC_MAX11115_CHANNELS)
465 #undef DT_DRV_COMPAT
466 
467 #define DT_DRV_COMPAT           maxim_max11116
468 #define ADC_MAX11116_RESOLUTION 8
469 #define ADC_MAX11116_CHANNELS   1
470 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
471 				  ADC_MAX11116_RESOLUTION, ADC_MAX11116_CHANNELS)
472 #undef DT_DRV_COMPAT
473 
474 #define DT_DRV_COMPAT           maxim_max11117
475 #define ADC_MAX11117_RESOLUTION 10
476 #define ADC_MAX11117_CHANNELS   1
477 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_MAX11102_17_INST_DEFINE, DT_DRV_COMPAT,
478 				  ADC_MAX11117_RESOLUTION, ADC_MAX11117_CHANNELS)
479 #undef DT_DRV_COMPAT
480