1 /*
2 * Copyright (c) 2023 SILA Embedded Solutions GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <zephyr/device.h>
7 #include <zephyr/devicetree.h>
8 #include <zephyr/drivers/adc.h>
9 #include <zephyr/drivers/adc/ads114s0x.h>
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/dt-bindings/adc/ads114s0x_adc.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/sys/__assert.h>
16 #include <zephyr/sys/byteorder.h>
17 #include <zephyr/sys/util.h>
18
19 #define ADC_CONTEXT_USES_KERNEL_TIMER 1
20 #define ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT \
21 K_MSEC(CONFIG_ADC_ADS114S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS)
22 #include "adc_context.h"
23
24 LOG_MODULE_REGISTER(ads114s0x, CONFIG_ADC_LOG_LEVEL);
25
26 #define ADS114S0X_CLK_FREQ_IN_KHZ 4096
27 #define ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES 4
28 #define ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES 4
29 #define ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES 32
30 #define ADS114S0X_INPUT_SELECTION_AINCOM 12
31 #define ADS114S0X_RESOLUTION 16
32 #define ADS114S0X_REF_INTERNAL 2500
33 #define ADS114S0X_GPIO_MAX 3
34 #define ADS114S0X_POWER_ON_RESET_TIME_IN_US 2200
35 #define ADS114S0X_VBIAS_PIN_MAX 7
36 #define ADS114S0X_VBIAS_PIN_MIN 0
37
38 /* Not mentioned in the datasheet, but instead determined experimentally. */
39 #define ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000
40 #define ADS114S0X_RESET_DELAY_TIME_IN_US \
41 (4096 * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ + ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US)
42
43 #define ADS114S0X_RESET_LOW_TIME_IN_US \
44 (ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
45 #define ADS114S0X_START_SYNC_PULSE_DURATION_IN_US \
46 (ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
47 #define ADS114S0X_SETUP_TIME_IN_US \
48 (ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
49
50 enum ads114s0x_command {
51 ADS114S0X_COMMAND_NOP = 0x00,
52 ADS114S0X_COMMAND_WAKEUP = 0x02,
53 ADS114S0X_COMMAND_POWERDOWN = 0x04,
54 ADS114S0X_COMMAND_RESET = 0x06,
55 ADS114S0X_COMMAND_START = 0x08,
56 ADS114S0X_COMMAND_STOP = 0x0A,
57 ADS114S0X_COMMAND_SYOCAL = 0x16,
58 ADS114S0X_COMMAND_SYGCAL = 0x17,
59 ADS114S0X_COMMAND_SFOCAL = 0x19,
60 ADS114S0X_COMMAND_RDATA = 0x12,
61 ADS114S0X_COMMAND_RREG = 0x20,
62 ADS114S0X_COMMAND_WREG = 0x40,
63 };
64
65 enum ads114s0x_register {
66 ADS114S0X_REGISTER_ID = 0x00,
67 ADS114S0X_REGISTER_STATUS = 0x01,
68 ADS114S0X_REGISTER_INPMUX = 0x02,
69 ADS114S0X_REGISTER_PGA = 0x03,
70 ADS114S0X_REGISTER_DATARATE = 0x04,
71 ADS114S0X_REGISTER_REF = 0x05,
72 ADS114S0X_REGISTER_IDACMAG = 0x06,
73 ADS114S0X_REGISTER_IDACMUX = 0x07,
74 ADS114S0X_REGISTER_VBIAS = 0x08,
75 ADS114S0X_REGISTER_SYS = 0x09,
76 ADS114S0X_REGISTER_OFCAL0 = 0x0B,
77 ADS114S0X_REGISTER_OFCAL1 = 0x0C,
78 ADS114S0X_REGISTER_FSCAL0 = 0x0E,
79 ADS114S0X_REGISTER_FSCAL1 = 0x0F,
80 ADS114S0X_REGISTER_GPIODAT = 0x10,
81 ADS114S0X_REGISTER_GPIOCON = 0x11,
82 };
83
84 #define ADS114S0X_REGISTER_GET_VALUE(value, pos, length) \
85 FIELD_GET(GENMASK(pos + length - 1, pos), value)
86 #define ADS114S0X_REGISTER_SET_VALUE(target, value, pos, length) \
87 target &= ~GENMASK(pos + length - 1, pos); \
88 target |= FIELD_PREP(GENMASK(pos + length - 1, pos), value)
89
90 #define ADS114S0X_REGISTER_ID_DEV_ID_LENGTH 3
91 #define ADS114S0X_REGISTER_ID_DEV_ID_POS 0
92 #define ADS114S0X_REGISTER_ID_DEV_ID_GET(value) \
93 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_ID_DEV_ID_POS, \
94 ADS114S0X_REGISTER_ID_DEV_ID_LENGTH)
95 #define ADS114S0X_REGISTER_ID_DEV_ID_SET(target, value) \
96 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_ID_DEV_ID_POS, \
97 ADS114S0X_REGISTER_ID_DEV_ID_LENGTH)
98 #define ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH 1
99 #define ADS114S0X_REGISTER_STATUS_FL_POR_POS 7
100 #define ADS114S0X_REGISTER_STATUS_FL_POR_GET(value) \
101 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_POR_POS, \
102 ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH)
103 #define ADS114S0X_REGISTER_STATUS_FL_POR_SET(target, value) \
104 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_POR_POS, \
105 ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH)
106 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH 1
107 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_POS 6
108 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(value) \
109 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS, \
110 ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
111 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_SET(target, value) \
112 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS, \
113 ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
114 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH 1
115 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS 5
116 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_GET(value) \
117 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS, \
118 ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
119 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_SET(target, value) \
120 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS, \
121 ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
122 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH 1
123 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS 4
124 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_GET(value) \
125 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS, \
126 ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
127 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_SET(target, value) \
128 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS, \
129 ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
130 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH 1
131 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS 3
132 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_GET(value) \
133 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS, \
134 ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
135 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_SET(target, value) \
136 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS, \
137 ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
138 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH 1
139 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS 2
140 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_GET(value) \
141 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS, \
142 ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
143 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_SET(target, value) \
144 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS, \
145 ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
146 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH 1
147 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS 1
148 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_GET(value) \
149 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS, \
150 ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
151 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_SET(target, value) \
152 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS, \
153 ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
154 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH 1
155 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS 0
156 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_GET(value) \
157 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS, \
158 ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
159 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_SET(target, value) \
160 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS, \
161 ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
162 #define ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH 4
163 #define ADS114S0X_REGISTER_INPMUX_MUXP_POS 4
164 #define ADS114S0X_REGISTER_INPMUX_MUXP_GET(value) \
165 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXP_POS, \
166 ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH)
167 #define ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, value) \
168 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXP_POS, \
169 ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH)
170 #define ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH 4
171 #define ADS114S0X_REGISTER_INPMUX_MUXN_POS 0
172 #define ADS114S0X_REGISTER_INPMUX_MUXN_GET(value) \
173 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXN_POS, \
174 ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH)
175 #define ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, value) \
176 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXN_POS, \
177 ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH)
178 #define ADS114S0X_REGISTER_PGA_DELAY_LENGTH 3
179 #define ADS114S0X_REGISTER_PGA_DELAY_POS 5
180 #define ADS114S0X_REGISTER_PGA_DELAY_GET(value) \
181 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_DELAY_POS, \
182 ADS114S0X_REGISTER_PGA_DELAY_LENGTH)
183 #define ADS114S0X_REGISTER_PGA_DELAY_SET(target, value) \
184 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_DELAY_POS, \
185 ADS114S0X_REGISTER_PGA_DELAY_LENGTH)
186 #define ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH 2
187 #define ADS114S0X_REGISTER_PGA_PGA_EN_POS 3
188 #define ADS114S0X_REGISTER_PGA_PGA_EN_GET(value) \
189 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_PGA_EN_POS, \
190 ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH)
191 #define ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, value) \
192 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_PGA_EN_POS, \
193 ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH)
194 #define ADS114S0X_REGISTER_PGA_GAIN_LENGTH 3
195 #define ADS114S0X_REGISTER_PGA_GAIN_POS 0
196 #define ADS114S0X_REGISTER_PGA_GAIN_GET(value) \
197 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_GAIN_POS, \
198 ADS114S0X_REGISTER_PGA_GAIN_LENGTH)
199 #define ADS114S0X_REGISTER_PGA_GAIN_SET(target, value) \
200 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_GAIN_POS, \
201 ADS114S0X_REGISTER_PGA_GAIN_LENGTH)
202 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH 1
203 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_POS 7
204 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_GET(value) \
205 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS, \
206 ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
207 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, value) \
208 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS, \
209 ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
210 #define ADS114S0X_REGISTER_DATARATE_CLK_LENGTH 1
211 #define ADS114S0X_REGISTER_DATARATE_CLK_POS 6
212 #define ADS114S0X_REGISTER_DATARATE_CLK_GET(value) \
213 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_CLK_POS, \
214 ADS114S0X_REGISTER_DATARATE_CLK_LENGTH)
215 #define ADS114S0X_REGISTER_DATARATE_CLK_SET(target, value) \
216 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_CLK_POS, \
217 ADS114S0X_REGISTER_DATARATE_CLK_LENGTH)
218 #define ADS114S0X_REGISTER_DATARATE_MODE_LENGTH 1
219 #define ADS114S0X_REGISTER_DATARATE_MODE_POS 5
220 #define ADS114S0X_REGISTER_DATARATE_MODE_GET(value) \
221 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_MODE_POS, \
222 ADS114S0X_REGISTER_DATARATE_MODE_LENGTH)
223 #define ADS114S0X_REGISTER_DATARATE_MODE_SET(target, value) \
224 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_MODE_POS, \
225 ADS114S0X_REGISTER_DATARATE_MODE_LENGTH)
226 #define ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH 1
227 #define ADS114S0X_REGISTER_DATARATE_FILTER_POS 4
228 #define ADS114S0X_REGISTER_DATARATE_FILTER_GET(value) \
229 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_FILTER_POS, \
230 ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH)
231 #define ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, value) \
232 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_FILTER_POS, \
233 ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH)
234 #define ADS114S0X_REGISTER_DATARATE_DR_LENGTH 4
235 #define ADS114S0X_REGISTER_DATARATE_DR_POS 0
236 #define ADS114S0X_REGISTER_DATARATE_DR_GET(value) \
237 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_DR_POS, \
238 ADS114S0X_REGISTER_DATARATE_DR_LENGTH)
239 #define ADS114S0X_REGISTER_DATARATE_DR_SET(target, value) \
240 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_DR_POS, \
241 ADS114S0X_REGISTER_DATARATE_DR_LENGTH)
242 #define ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH 2
243 #define ADS114S0X_REGISTER_REF_FL_REF_EN_POS 6
244 #define ADS114S0X_REGISTER_REF_FL_REF_EN_GET(value) \
245 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS, \
246 ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH)
247 #define ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, value) \
248 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS, \
249 ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH)
250 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH 1
251 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS 5
252 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_GET(value) \
253 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS, \
254 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
255 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, value) \
256 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS, \
257 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
258 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH 1
259 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS 4
260 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_GET(value) \
261 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS, \
262 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
263 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, value) \
264 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS, \
265 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
266 #define ADS114S0X_REGISTER_REF_REFSEL_LENGTH 2
267 #define ADS114S0X_REGISTER_REF_REFSEL_POS 2
268 #define ADS114S0X_REGISTER_REF_REFSEL_GET(value) \
269 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFSEL_POS, \
270 ADS114S0X_REGISTER_REF_REFSEL_LENGTH)
271 #define ADS114S0X_REGISTER_REF_REFSEL_SET(target, value) \
272 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFSEL_POS, \
273 ADS114S0X_REGISTER_REF_REFSEL_LENGTH)
274 #define ADS114S0X_REGISTER_REF_REFCON_LENGTH 2
275 #define ADS114S0X_REGISTER_REF_REFCON_POS 0
276 #define ADS114S0X_REGISTER_REF_REFCON_GET(value) \
277 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFCON_POS, \
278 ADS114S0X_REGISTER_REF_REFCON_LENGTH)
279 #define ADS114S0X_REGISTER_REF_REFCON_SET(target, value) \
280 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFCON_POS, \
281 ADS114S0X_REGISTER_REF_REFCON_LENGTH)
282 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH 1
283 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS 7
284 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_GET(value) \
285 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \
286 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
287 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, value) \
288 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \
289 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
290 #define ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH 1
291 #define ADS114S0X_REGISTER_IDACMAG_PSW_POS 6
292 #define ADS114S0X_REGISTER_IDACMAG_PSW_GET(value) \
293 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_PSW_POS, \
294 ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH)
295 #define ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, value) \
296 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_PSW_POS, \
297 ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH)
298 #define ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH 4
299 #define ADS114S0X_REGISTER_IDACMAG_IMAG_POS 0
300 #define ADS114S0X_REGISTER_IDACMAG_IMAG_GET(value) \
301 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS, \
302 ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH)
303 #define ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, value) \
304 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS, \
305 ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH)
306 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH 4
307 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_POS 4
308 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_GET(value) \
309 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS, \
310 ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
311 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, value) \
312 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS, \
313 ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
314 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH 4
315 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_POS 0
316 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_GET(value) \
317 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \
318 ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
319 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, value) \
320 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \
321 ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
322 #define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH 1
323 #define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS 7
324 #define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_GET(value) \
325 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS, \
326 ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH)
327 #define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(target, value) \
328 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS, \
329 ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH)
330 #define ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH 4
331 #define ADS114S0X_REGISTER_GPIODAT_DIR_POS 4
332 #define ADS114S0X_REGISTER_GPIODAT_DIR_GET(value) \
333 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DIR_POS, \
334 ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH)
335 #define ADS114S0X_REGISTER_GPIODAT_DIR_SET(target, value) \
336 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DIR_POS, \
337 ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH)
338 #define ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH 4
339 #define ADS114S0X_REGISTER_GPIODAT_DAT_POS 0
340 #define ADS114S0X_REGISTER_GPIODAT_DAT_GET(value) \
341 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DAT_POS, \
342 ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH)
343 #define ADS114S0X_REGISTER_GPIODAT_DAT_SET(target, value) \
344 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DAT_POS, \
345 ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH)
346 #define ADS114S0X_REGISTER_GPIOCON_CON_LENGTH 4
347 #define ADS114S0X_REGISTER_GPIOCON_CON_POS 0
348 #define ADS114S0X_REGISTER_GPIOCON_CON_GET(value) \
349 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIOCON_CON_POS, \
350 ADS114S0X_REGISTER_GPIOCON_CON_LENGTH)
351 #define ADS114S0X_REGISTER_GPIOCON_CON_SET(target, value) \
352 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIOCON_CON_POS, \
353 ADS114S0X_REGISTER_GPIOCON_CON_LENGTH)
354
355 /*
356 * - AIN0 as positive input
357 * - AIN1 as negative input
358 */
359 #define ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(target) \
360 ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000); \
361 ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001)
362 /*
363 * - disable reference monitor
364 * - enable positive reference buffer
365 * - disable negative reference buffer
366 * - use internal reference
367 * - enable internal voltage reference
368 */
369 #define ADS114S0X_REGISTER_REF_SET_DEFAULTS(target) \
370 ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00); \
371 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0); \
372 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1); \
373 ADS114S0X_REGISTER_REF_REFSEL_SET(target, 0b10); \
374 ADS114S0X_REGISTER_REF_REFCON_SET(target, 0b01)
375 /*
376 * - disable global chop
377 * - use internal oscillator
378 * - single shot conversion mode
379 * - low latency filter
380 * - 20 samples per second
381 */
382 #define ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(target) \
383 ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0); \
384 ADS114S0X_REGISTER_DATARATE_CLK_SET(target, 0b0); \
385 ADS114S0X_REGISTER_DATARATE_MODE_SET(target, 0b1); \
386 ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1); \
387 ADS114S0X_REGISTER_DATARATE_DR_SET(target, 0b0100)
388 /*
389 * - delay of 14*t_mod
390 * - disable gain
391 * - gain 1
392 */
393 #define ADS114S0X_REGISTER_PGA_SET_DEFAULTS(target) \
394 ADS114S0X_REGISTER_PGA_DELAY_SET(target, 0b000); \
395 ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00); \
396 ADS114S0X_REGISTER_PGA_GAIN_SET(target, 0b000)
397 /*
398 * - disable PGA output rail flag
399 * - low-side power switch
400 * - IDAC off
401 */
402 #define ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(target) \
403 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0); \
404 ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0); \
405 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000)
406 /*
407 * - disconnect IDAC1
408 * - disconnect IDAC2
409 */
410 #define ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(target) \
411 ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111); \
412 ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111)
413
414 struct ads114s0x_config {
415 struct spi_dt_spec bus;
416 #if CONFIG_ADC_ASYNC
417 k_thread_stack_t *stack;
418 #endif
419 const struct gpio_dt_spec gpio_reset;
420 const struct gpio_dt_spec gpio_data_ready;
421 const struct gpio_dt_spec gpio_start_sync;
422 int idac_current;
423 uint8_t vbias_level;
424 };
425
426 struct ads114s0x_data {
427 struct adc_context ctx;
428 #if CONFIG_ADC_ASYNC
429 struct k_thread thread;
430 #endif /* CONFIG_ADC_ASYNC */
431 struct gpio_callback callback_data_ready;
432 struct k_sem data_ready_signal;
433 struct k_sem acquire_signal;
434 int16_t *buffer;
435 int16_t *buffer_ptr;
436 #if CONFIG_ADC_ADS114S0X_GPIO
437 struct k_mutex gpio_lock;
438 uint8_t gpio_enabled; /* one bit per GPIO, 1 = enabled */
439 uint8_t gpio_direction; /* one bit per GPIO, 1 = input */
440 uint8_t gpio_value; /* one bit per GPIO, 1 = high */
441 #endif /* CONFIG_ADC_ADS114S0X_GPIO */
442 };
443
ads114s0x_data_ready_handler(const struct device * dev,struct gpio_callback * gpio_cb,uint32_t pins)444 static void ads114s0x_data_ready_handler(const struct device *dev, struct gpio_callback *gpio_cb,
445 uint32_t pins)
446 {
447 ARG_UNUSED(dev);
448 ARG_UNUSED(pins);
449
450 struct ads114s0x_data *data =
451 CONTAINER_OF(gpio_cb, struct ads114s0x_data, callback_data_ready);
452
453 k_sem_give(&data->data_ready_signal);
454 }
455
ads114s0x_read_register(const struct device * dev,enum ads114s0x_register register_address,uint8_t * value)456 static int ads114s0x_read_register(const struct device *dev,
457 enum ads114s0x_register register_address, uint8_t *value)
458 {
459 const struct ads114s0x_config *config = dev->config;
460 uint8_t buffer_tx[3];
461 uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
462 const struct spi_buf tx_buf[] = {{
463 .buf = buffer_tx,
464 .len = ARRAY_SIZE(buffer_tx),
465 }};
466 const struct spi_buf rx_buf[] = {{
467 .buf = buffer_rx,
468 .len = ARRAY_SIZE(buffer_rx),
469 }};
470 const struct spi_buf_set tx = {
471 .buffers = tx_buf,
472 .count = ARRAY_SIZE(tx_buf),
473 };
474 const struct spi_buf_set rx = {
475 .buffers = rx_buf,
476 .count = ARRAY_SIZE(rx_buf),
477 };
478
479 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_RREG) | ((uint8_t)register_address);
480 /* read one register */
481 buffer_tx[1] = 0x00;
482
483 int result = spi_transceive_dt(&config->bus, &tx, &rx);
484
485 if (result != 0) {
486 LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
487 return result;
488 }
489
490 *value = buffer_rx[2];
491 LOG_DBG("%s: read from register 0x%02X value 0x%02X", dev->name, register_address, *value);
492
493 return 0;
494 }
495
ads114s0x_write_register(const struct device * dev,enum ads114s0x_register register_address,uint8_t value)496 static int ads114s0x_write_register(const struct device *dev,
497 enum ads114s0x_register register_address, uint8_t value)
498 {
499 const struct ads114s0x_config *config = dev->config;
500 uint8_t buffer_tx[3];
501 const struct spi_buf tx_buf[] = {{
502 .buf = buffer_tx,
503 .len = ARRAY_SIZE(buffer_tx),
504 }};
505 const struct spi_buf_set tx = {
506 .buffers = tx_buf,
507 .count = ARRAY_SIZE(tx_buf),
508 };
509
510 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_address);
511 /* write one register */
512 buffer_tx[1] = 0x00;
513 buffer_tx[2] = value;
514
515 LOG_DBG("%s: writing to register 0x%02X value 0x%02X", dev->name, register_address, value);
516 int result = spi_write_dt(&config->bus, &tx);
517
518 if (result != 0) {
519 LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
520 return result;
521 }
522
523 return 0;
524 }
525
ads114s0x_write_multiple_registers(const struct device * dev,enum ads114s0x_register * register_addresses,uint8_t * values,size_t count)526 static int ads114s0x_write_multiple_registers(const struct device *dev,
527 enum ads114s0x_register *register_addresses,
528 uint8_t *values, size_t count)
529 {
530 const struct ads114s0x_config *config = dev->config;
531 uint8_t buffer_tx[2];
532 const struct spi_buf tx_buf[] = {
533 {
534 .buf = buffer_tx,
535 .len = ARRAY_SIZE(buffer_tx),
536 },
537 {
538 .buf = values,
539 .len = count,
540 },
541 };
542 const struct spi_buf_set tx = {
543 .buffers = tx_buf,
544 .count = ARRAY_SIZE(tx_buf),
545 };
546
547 if (count == 0) {
548 LOG_WRN("%s: ignoring the command to write 0 registers", dev->name);
549 return -EINVAL;
550 }
551
552 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]);
553 buffer_tx[1] = count - 1;
554
555 LOG_HEXDUMP_DBG(register_addresses, count, "writing to registers");
556 LOG_HEXDUMP_DBG(values, count, "values");
557
558 /* ensure that the register addresses are in the correct order */
559 for (size_t i = 1; i < count; ++i) {
560 __ASSERT(register_addresses[i - 1] + 1 == register_addresses[i],
561 "register addresses are not consecutive");
562 }
563
564 int result = spi_write_dt(&config->bus, &tx);
565
566 if (result != 0) {
567 LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
568 return result;
569 }
570
571 return 0;
572 }
573
ads114s0x_send_command(const struct device * dev,enum ads114s0x_command command)574 static int ads114s0x_send_command(const struct device *dev, enum ads114s0x_command command)
575 {
576 const struct ads114s0x_config *config = dev->config;
577 uint8_t buffer_tx[1];
578 const struct spi_buf tx_buf[] = {{
579 .buf = buffer_tx,
580 .len = ARRAY_SIZE(buffer_tx),
581 }};
582 const struct spi_buf_set tx = {
583 .buffers = tx_buf,
584 .count = ARRAY_SIZE(tx_buf),
585 };
586
587 buffer_tx[0] = (uint8_t)command;
588
589 LOG_DBG("%s: sending command 0x%02X", dev->name, command);
590 int result = spi_write_dt(&config->bus, &tx);
591
592 if (result != 0) {
593 LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
594 return result;
595 }
596
597 return 0;
598 }
599
ads114s0x_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)600 static int ads114s0x_channel_setup(const struct device *dev,
601 const struct adc_channel_cfg *channel_cfg)
602 {
603 const struct ads114s0x_config *config = dev->config;
604 uint8_t input_mux = 0;
605 uint8_t reference_control = 0;
606 uint8_t data_rate = 0;
607 uint8_t gain = 0;
608 uint8_t idac_magnitude = 0;
609 uint8_t idac_mux = 0;
610 uint8_t pin_selections[4];
611 uint8_t vbias = 0;
612 size_t pin_selections_size;
613 int result;
614 enum ads114s0x_register register_addresses[7];
615 uint8_t values[ARRAY_SIZE(register_addresses)];
616 uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
617 uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time);
618
619 ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(gain);
620 ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
621 ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(data_rate);
622 ADS114S0X_REGISTER_PGA_SET_DEFAULTS(gain);
623 ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(idac_magnitude);
624 ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(idac_mux);
625
626 if (channel_cfg->channel_id != 0) {
627 LOG_ERR("%s: only one channel is supported", dev->name);
628 return -EINVAL;
629 }
630
631 /* The ADS114 uses samples per seconds units with the lowest being 2.5SPS
632 * and with acquisition_time only having 14b for time, this will not fit
633 * within here for microsecond units. Use Tick units and allow the user to
634 * specify the ODR directly.
635 */
636 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT &&
637 acquisition_time_unit != ADC_ACQ_TIME_TICKS) {
638 LOG_ERR("%s: invalid acquisition time %i", dev->name,
639 channel_cfg->acquisition_time);
640 return -EINVAL;
641 }
642
643 if (channel_cfg->acquisition_time == ADC_ACQ_TIME_DEFAULT) {
644 ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, ADS114S0X_CONFIG_DR_20);
645 } else {
646 ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, acquisition_time_value);
647 }
648
649 switch (channel_cfg->reference) {
650 case ADC_REF_INTERNAL:
651 /* disable negative reference buffer */
652 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1);
653 /* disable positive reference buffer */
654 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1);
655 /* use internal reference */
656 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10);
657 break;
658 case ADC_REF_EXTERNAL0:
659 /* enable negative reference buffer */
660 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
661 /* enable positive reference buffer */
662 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
663 /* use external reference 0*/
664 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00);
665 break;
666 case ADC_REF_EXTERNAL1:
667 /* enable negative reference buffer */
668 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
669 /* enable positive reference buffer */
670 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
671 /* use external reference 0*/
672 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01);
673 break;
674 default:
675 LOG_ERR("%s: reference %i is not supported", dev->name, channel_cfg->reference);
676 return -EINVAL;
677 }
678
679 if (channel_cfg->differential) {
680 LOG_DBG("%s: configuring channel for a differential measurement from the pins (p, "
681 "n) (%i, %i)",
682 dev->name, channel_cfg->input_positive, channel_cfg->input_negative);
683 if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) {
684 LOG_ERR("%s: positive channel input %i is invalid", dev->name,
685 channel_cfg->input_positive);
686 return -EINVAL;
687 }
688
689 if (channel_cfg->input_negative >= ADS114S0X_INPUT_SELECTION_AINCOM) {
690 LOG_ERR("%s: negative channel input %i is invalid", dev->name,
691 channel_cfg->input_negative);
692 return -EINVAL;
693 }
694
695 if (channel_cfg->input_positive == channel_cfg->input_negative) {
696 LOG_ERR("%s: negative and positive channel inputs must be different",
697 dev->name);
698 return -EINVAL;
699 }
700
701 ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
702 ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative);
703 pin_selections[0] = channel_cfg->input_positive;
704 pin_selections[1] = channel_cfg->input_negative;
705 } else {
706 LOG_DBG("%s: configuring channel for single ended measurement from input %i",
707 dev->name, channel_cfg->input_positive);
708 if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) {
709 LOG_ERR("%s: channel input %i is invalid", dev->name,
710 channel_cfg->input_positive);
711 return -EINVAL;
712 }
713
714 ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
715 ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, ADS114S0X_INPUT_SELECTION_AINCOM);
716 pin_selections[0] = channel_cfg->input_positive;
717 pin_selections[1] = ADS114S0X_INPUT_SELECTION_AINCOM;
718 }
719
720 switch (channel_cfg->gain) {
721 case ADC_GAIN_1:
722 /* set gain value */
723 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b000);
724 break;
725 case ADC_GAIN_2:
726 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b001);
727 break;
728 case ADC_GAIN_4:
729 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b010);
730 break;
731 case ADC_GAIN_8:
732 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b011);
733 break;
734 case ADC_GAIN_16:
735 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b100);
736 break;
737 case ADC_GAIN_32:
738 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b101);
739 break;
740 case ADC_GAIN_64:
741 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b110);
742 break;
743 case ADC_GAIN_128:
744 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b111);
745 break;
746 default:
747 LOG_ERR("%s: gain value %i not supported", dev->name, channel_cfg->gain);
748 return -EINVAL;
749 }
750
751 if (channel_cfg->gain != ADC_GAIN_1) {
752 /* enable gain */
753 ADS114S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01);
754 }
755
756 switch (config->idac_current) {
757 case 0:
758 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000);
759 break;
760 case 10:
761 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001);
762 break;
763 case 50:
764 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010);
765 break;
766 case 100:
767 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011);
768 break;
769 case 250:
770 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100);
771 break;
772 case 500:
773 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101);
774 break;
775 case 750:
776 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110);
777 break;
778 case 1000:
779 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111);
780 break;
781 case 1500:
782 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000);
783 break;
784 case 2000:
785 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001);
786 break;
787 default:
788 LOG_ERR("%s: IDAC magnitude %i not supported", dev->name, config->idac_current);
789 return -EINVAL;
790 }
791
792 if (channel_cfg->current_source_pin_set) {
793 LOG_DBG("%s: current source pin set to %i and %i", dev->name,
794 channel_cfg->current_source_pin[0], channel_cfg->current_source_pin[1]);
795 if (channel_cfg->current_source_pin[0] > 0b1111) {
796 LOG_ERR("%s: invalid selection %i for I1MUX", dev->name,
797 channel_cfg->current_source_pin[0]);
798 return -EINVAL;
799 }
800
801 if (channel_cfg->current_source_pin[1] > 0b1111) {
802 LOG_ERR("%s: invalid selection %i for I2MUX", dev->name,
803 channel_cfg->current_source_pin[1]);
804 return -EINVAL;
805 }
806
807 ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]);
808 ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]);
809 pin_selections[2] = channel_cfg->current_source_pin[0];
810 pin_selections[3] = channel_cfg->current_source_pin[1];
811 pin_selections_size = 4;
812 } else {
813 LOG_DBG("%s: current source pins not set", dev->name);
814 pin_selections_size = 2;
815 }
816
817 for (size_t i = 0; i < pin_selections_size; ++i) {
818 if (pin_selections[i] > ADS114S0X_INPUT_SELECTION_AINCOM) {
819 continue;
820 }
821
822 for (size_t j = i + 1; j < pin_selections_size; ++j) {
823 if (pin_selections[j] > ADS114S0X_INPUT_SELECTION_AINCOM) {
824 continue;
825 }
826
827 if (pin_selections[i] == pin_selections[j]) {
828 LOG_ERR("%s: pins for inputs and current sources must be different",
829 dev->name);
830 return -EINVAL;
831 }
832 }
833 }
834
835 ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level);
836
837 if ((channel_cfg->vbias_pins &
838 ~GENMASK(ADS114S0X_VBIAS_PIN_MAX, ADS114S0X_VBIAS_PIN_MIN)) != 0) {
839 LOG_ERR("%s: invalid VBIAS pin selection 0x%08X", dev->name,
840 channel_cfg->vbias_pins);
841 return -EINVAL;
842 }
843
844 vbias |= channel_cfg->vbias_pins;
845
846 register_addresses[0] = ADS114S0X_REGISTER_INPMUX;
847 register_addresses[1] = ADS114S0X_REGISTER_PGA;
848 register_addresses[2] = ADS114S0X_REGISTER_DATARATE;
849 register_addresses[3] = ADS114S0X_REGISTER_REF;
850 register_addresses[4] = ADS114S0X_REGISTER_IDACMAG;
851 register_addresses[5] = ADS114S0X_REGISTER_IDACMUX;
852 register_addresses[6] = ADS114S0X_REGISTER_VBIAS;
853 BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 7);
854 values[0] = input_mux;
855 values[1] = gain;
856 values[2] = data_rate;
857 values[3] = reference_control;
858 values[4] = idac_magnitude;
859 values[5] = idac_mux;
860 values[6] = vbias;
861 BUILD_ASSERT(ARRAY_SIZE(values) == 7);
862
863 result = ads114s0x_write_multiple_registers(dev, register_addresses, values,
864 ARRAY_SIZE(values));
865
866 if (result != 0) {
867 LOG_ERR("%s: unable to configure registers", dev->name);
868 return result;
869 }
870
871 return 0;
872 }
873
ads114s0x_validate_buffer_size(const struct adc_sequence * sequence)874 static int ads114s0x_validate_buffer_size(const struct adc_sequence *sequence)
875 {
876 size_t needed = sizeof(int16_t);
877
878 if (sequence->options) {
879 needed *= (1 + sequence->options->extra_samplings);
880 }
881
882 if (sequence->buffer_size < needed) {
883 return -ENOMEM;
884 }
885
886 return 0;
887 }
888
ads114s0x_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)889 static int ads114s0x_validate_sequence(const struct device *dev,
890 const struct adc_sequence *sequence)
891 {
892 if (sequence->resolution != ADS114S0X_RESOLUTION) {
893 LOG_ERR("%s: invalid resolution", dev->name);
894 return -EINVAL;
895 }
896
897 if (sequence->channels != BIT(0)) {
898 LOG_ERR("%s: invalid channel", dev->name);
899 return -EINVAL;
900 }
901
902 if (sequence->oversampling) {
903 LOG_ERR("%s: oversampling is not supported", dev->name);
904 return -EINVAL;
905 }
906
907 return ads114s0x_validate_buffer_size(sequence);
908 }
909
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)910 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
911 {
912 struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx);
913
914 if (repeat_sampling) {
915 data->buffer = data->buffer_ptr;
916 }
917 }
918
adc_context_start_sampling(struct adc_context * ctx)919 static void adc_context_start_sampling(struct adc_context *ctx)
920 {
921 struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx);
922
923 data->buffer_ptr = data->buffer;
924 k_sem_give(&data->acquire_signal);
925 }
926
ads114s0x_adc_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)927 static int ads114s0x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
928 bool wait)
929 {
930 int result;
931 struct ads114s0x_data *data = dev->data;
932
933 result = ads114s0x_validate_sequence(dev, sequence);
934
935 if (result != 0) {
936 LOG_ERR("%s: sequence validation failed", dev->name);
937 return result;
938 }
939
940 data->buffer = sequence->buffer;
941
942 adc_context_start_read(&data->ctx, sequence);
943
944 if (wait) {
945 result = adc_context_wait_for_completion(&data->ctx);
946 }
947
948 return result;
949 }
950
ads114s0x_send_start_read(const struct device * dev)951 static int ads114s0x_send_start_read(const struct device *dev)
952 {
953 const struct ads114s0x_config *config = dev->config;
954 int result;
955
956 if (config->gpio_start_sync.port == 0) {
957 result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_START);
958 if (result != 0) {
959 LOG_ERR("%s: unable to send START/SYNC command", dev->name);
960 return result;
961 }
962 } else {
963 result = gpio_pin_set_dt(&config->gpio_start_sync, 1);
964
965 if (result != 0) {
966 LOG_ERR("%s: unable to start ADC operation", dev->name);
967 return result;
968 }
969
970 k_sleep(K_USEC(ADS114S0X_START_SYNC_PULSE_DURATION_IN_US +
971 ADS114S0X_SETUP_TIME_IN_US));
972
973 result = gpio_pin_set_dt(&config->gpio_start_sync, 0);
974
975 if (result != 0) {
976 LOG_ERR("%s: unable to start ADC operation", dev->name);
977 return result;
978 }
979 }
980
981 return 0;
982 }
983
ads114s0x_wait_data_ready(const struct device * dev)984 static int ads114s0x_wait_data_ready(const struct device *dev)
985 {
986 struct ads114s0x_data *data = dev->data;
987
988 return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT);
989 }
990
ads114s0x_read_sample(const struct device * dev,uint16_t * buffer)991 static int ads114s0x_read_sample(const struct device *dev, uint16_t *buffer)
992 {
993 const struct ads114s0x_config *config = dev->config;
994 uint8_t buffer_tx[3];
995 uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
996 const struct spi_buf tx_buf[] = {{
997 .buf = buffer_tx,
998 .len = ARRAY_SIZE(buffer_tx),
999 }};
1000 const struct spi_buf rx_buf[] = {{
1001 .buf = buffer_rx,
1002 .len = ARRAY_SIZE(buffer_rx),
1003 }};
1004 const struct spi_buf_set tx = {
1005 .buffers = tx_buf,
1006 .count = ARRAY_SIZE(tx_buf),
1007 };
1008 const struct spi_buf_set rx = {
1009 .buffers = rx_buf,
1010 .count = ARRAY_SIZE(rx_buf),
1011 };
1012
1013 buffer_tx[0] = (uint8_t)ADS114S0X_COMMAND_RDATA;
1014
1015 int result = spi_transceive_dt(&config->bus, &tx, &rx);
1016
1017 if (result != 0) {
1018 LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
1019 return result;
1020 }
1021
1022 *buffer = sys_get_be16(buffer_rx + 1);
1023 LOG_DBG("%s: read ADC sample %i", dev->name, *buffer);
1024
1025 return 0;
1026 }
1027
ads114s0x_adc_perform_read(const struct device * dev)1028 static int ads114s0x_adc_perform_read(const struct device *dev)
1029 {
1030 int result;
1031 struct ads114s0x_data *data = dev->data;
1032
1033 k_sem_take(&data->acquire_signal, K_FOREVER);
1034 k_sem_reset(&data->data_ready_signal);
1035
1036 result = ads114s0x_send_start_read(dev);
1037 if (result != 0) {
1038 LOG_ERR("%s: unable to start ADC conversion", dev->name);
1039 adc_context_complete(&data->ctx, result);
1040 return result;
1041 }
1042
1043 result = ads114s0x_wait_data_ready(dev);
1044 if (result != 0) {
1045 LOG_ERR("%s: waiting for data to be ready failed", dev->name);
1046 adc_context_complete(&data->ctx, result);
1047 return result;
1048 }
1049
1050 result = ads114s0x_read_sample(dev, data->buffer);
1051 if (result != 0) {
1052 LOG_ERR("%s: reading sample failed", dev->name);
1053 adc_context_complete(&data->ctx, result);
1054 return result;
1055 }
1056
1057 data->buffer++;
1058
1059 adc_context_on_sampling_done(&data->ctx, dev);
1060
1061 return result;
1062 }
1063
1064 #if CONFIG_ADC_ASYNC
ads114s0x_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)1065 static int ads114s0x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
1066 struct k_poll_signal *async)
1067 {
1068 int result;
1069 struct ads114s0x_data *data = dev->data;
1070
1071 adc_context_lock(&data->ctx, true, async);
1072 result = ads114s0x_adc_start_read(dev, sequence, true);
1073 adc_context_release(&data->ctx, result);
1074
1075 return result;
1076 }
1077
ads114s0x_read(const struct device * dev,const struct adc_sequence * sequence)1078 static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence)
1079 {
1080 int result;
1081 struct ads114s0x_data *data = dev->data;
1082
1083 adc_context_lock(&data->ctx, false, NULL);
1084 result = ads114s0x_adc_start_read(dev, sequence, true);
1085 adc_context_release(&data->ctx, result);
1086
1087 return result;
1088 }
1089
1090 #else
ads114s0x_read(const struct device * dev,const struct adc_sequence * sequence)1091 static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence)
1092 {
1093 int result;
1094 struct ads114s0x_data *data = dev->data;
1095
1096 adc_context_lock(&data->ctx, false, NULL);
1097 result = ads114s0x_adc_start_read(dev, sequence, false);
1098
1099 while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
1100 result = ads114s0x_adc_perform_read(dev);
1101 }
1102
1103 adc_context_release(&data->ctx, result);
1104 return result;
1105 }
1106 #endif
1107
1108 #if CONFIG_ADC_ASYNC
ads114s0x_acquisition_thread(void * p1,void * p2,void * p3)1109 static void ads114s0x_acquisition_thread(void *p1, void *p2, void *p3)
1110 {
1111 ARG_UNUSED(p2);
1112 ARG_UNUSED(p3);
1113
1114 const struct device *dev = p1;
1115 while (true) {
1116 ads114s0x_adc_perform_read(dev);
1117 }
1118 }
1119 #endif
1120
1121 #ifdef CONFIG_ADC_ADS114S0X_GPIO
ads114s0x_gpio_write_config(const struct device * dev)1122 static int ads114s0x_gpio_write_config(const struct device *dev)
1123 {
1124 struct ads114s0x_data *data = dev->data;
1125 enum ads114s0x_register register_addresses[2];
1126 uint8_t register_values[ARRAY_SIZE(register_addresses)];
1127 uint8_t gpio_dat = 0;
1128 uint8_t gpio_con = 0;
1129
1130 ADS114S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled);
1131 ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
1132 ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
1133
1134 register_values[0] = gpio_dat;
1135 register_values[1] = gpio_con;
1136 register_addresses[0] = ADS114S0X_REGISTER_GPIODAT;
1137 register_addresses[1] = ADS114S0X_REGISTER_GPIOCON;
1138 return ads114s0x_write_multiple_registers(dev, register_addresses, register_values,
1139 ARRAY_SIZE(register_values));
1140 }
1141
ads114s0x_gpio_write_value(const struct device * dev)1142 static int ads114s0x_gpio_write_value(const struct device *dev)
1143 {
1144 struct ads114s0x_data *data = dev->data;
1145 uint8_t gpio_dat = 0;
1146
1147 ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
1148 ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
1149
1150 return ads114s0x_write_register(dev, ADS114S0X_REGISTER_GPIODAT, gpio_dat);
1151 }
1152
ads114s0x_gpio_set_output(const struct device * dev,uint8_t pin,bool initial_value)1153 int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value)
1154 {
1155 struct ads114s0x_data *data = dev->data;
1156 int result = 0;
1157
1158 if (pin > ADS114S0X_GPIO_MAX) {
1159 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1160 return -EINVAL;
1161 }
1162
1163 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1164
1165 data->gpio_enabled |= BIT(pin);
1166 data->gpio_direction &= ~BIT(pin);
1167
1168 if (initial_value) {
1169 data->gpio_value |= BIT(pin);
1170 } else {
1171 data->gpio_value &= ~BIT(pin);
1172 }
1173
1174 result = ads114s0x_gpio_write_config(dev);
1175
1176 k_mutex_unlock(&data->gpio_lock);
1177
1178 return result;
1179 }
1180
ads114s0x_gpio_set_input(const struct device * dev,uint8_t pin)1181 int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin)
1182 {
1183 struct ads114s0x_data *data = dev->data;
1184 int result = 0;
1185
1186 if (pin > ADS114S0X_GPIO_MAX) {
1187 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1188 return -EINVAL;
1189 }
1190
1191 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1192
1193 data->gpio_enabled |= BIT(pin);
1194 data->gpio_direction |= BIT(pin);
1195 data->gpio_value &= ~BIT(pin);
1196
1197 result = ads114s0x_gpio_write_config(dev);
1198
1199 k_mutex_unlock(&data->gpio_lock);
1200
1201 return result;
1202 }
1203
ads114s0x_gpio_deconfigure(const struct device * dev,uint8_t pin)1204 int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin)
1205 {
1206 struct ads114s0x_data *data = dev->data;
1207 int result = 0;
1208
1209 if (pin > ADS114S0X_GPIO_MAX) {
1210 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1211 return -EINVAL;
1212 }
1213
1214 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1215
1216 data->gpio_enabled &= ~BIT(pin);
1217 data->gpio_direction |= BIT(pin);
1218 data->gpio_value &= ~BIT(pin);
1219
1220 result = ads114s0x_gpio_write_config(dev);
1221
1222 k_mutex_unlock(&data->gpio_lock);
1223
1224 return result;
1225 }
1226
ads114s0x_gpio_set_pin_value(const struct device * dev,uint8_t pin,bool value)1227 int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value)
1228 {
1229 struct ads114s0x_data *data = dev->data;
1230 int result = 0;
1231
1232 if (pin > ADS114S0X_GPIO_MAX) {
1233 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1234 return -EINVAL;
1235 }
1236
1237 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1238
1239 if ((BIT(pin) & data->gpio_enabled) == 0) {
1240 LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
1241 result = -EINVAL;
1242 } else if ((BIT(pin) & data->gpio_direction) != 0) {
1243 LOG_ERR("%s: gpio pin %i not configured as output", dev->name, pin);
1244 result = -EINVAL;
1245 } else {
1246 data->gpio_value |= BIT(pin);
1247
1248 result = ads114s0x_gpio_write_value(dev);
1249 }
1250
1251 k_mutex_unlock(&data->gpio_lock);
1252
1253 return result;
1254 }
1255
ads114s0x_gpio_get_pin_value(const struct device * dev,uint8_t pin,bool * value)1256 int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value)
1257 {
1258 struct ads114s0x_data *data = dev->data;
1259 int result = 0;
1260 uint8_t gpio_dat;
1261
1262 if (pin > ADS114S0X_GPIO_MAX) {
1263 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1264 return -EINVAL;
1265 }
1266
1267 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1268
1269 if ((BIT(pin) & data->gpio_enabled) == 0) {
1270 LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
1271 result = -EINVAL;
1272 } else if ((BIT(pin) & data->gpio_direction) == 0) {
1273 LOG_ERR("%s: gpio pin %i not configured as input", dev->name, pin);
1274 result = -EINVAL;
1275 } else {
1276 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat);
1277 data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
1278 *value = (BIT(pin) & data->gpio_value) != 0;
1279 }
1280
1281 k_mutex_unlock(&data->gpio_lock);
1282
1283 return result;
1284 }
1285
ads114s0x_gpio_port_get_raw(const struct device * dev,gpio_port_value_t * value)1286 int ads114s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
1287 {
1288 struct ads114s0x_data *data = dev->data;
1289 int result = 0;
1290 uint8_t gpio_dat;
1291
1292 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1293
1294 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat);
1295 data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
1296 *value = data->gpio_value;
1297
1298 k_mutex_unlock(&data->gpio_lock);
1299
1300 return result;
1301 }
1302
ads114s0x_gpio_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)1303 int ads114s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
1304 gpio_port_value_t value)
1305 {
1306 struct ads114s0x_data *data = dev->data;
1307 int result = 0;
1308
1309 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1310
1311 data->gpio_value = ((data->gpio_value & ~mask) | (mask & value)) & data->gpio_enabled &
1312 ~data->gpio_direction;
1313 result = ads114s0x_gpio_write_value(dev);
1314
1315 k_mutex_unlock(&data->gpio_lock);
1316
1317 return result;
1318 }
1319
ads114s0x_gpio_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)1320 int ads114s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
1321 {
1322 struct ads114s0x_data *data = dev->data;
1323 int result = 0;
1324
1325 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1326
1327 data->gpio_value = (data->gpio_value ^ pins) & data->gpio_enabled & ~data->gpio_direction;
1328 result = ads114s0x_gpio_write_value(dev);
1329
1330 k_mutex_unlock(&data->gpio_lock);
1331
1332 return result;
1333 }
1334
1335 #endif /* CONFIG_ADC_ADS114S0X_GPIO */
1336
ads114s0x_init(const struct device * dev)1337 static int ads114s0x_init(const struct device *dev)
1338 {
1339 uint8_t status = 0;
1340 uint8_t reference_control = 0;
1341 uint8_t reference_control_read;
1342 int result;
1343 const struct ads114s0x_config *config = dev->config;
1344 struct ads114s0x_data *data = dev->data;
1345
1346 adc_context_init(&data->ctx);
1347
1348 k_sem_init(&data->data_ready_signal, 0, 1);
1349 k_sem_init(&data->acquire_signal, 0, 1);
1350
1351 #ifdef CONFIG_ADC_ADS114S0X_GPIO
1352 k_mutex_init(&data->gpio_lock);
1353 #endif /* CONFIG_ADC_ADS114S0X_GPIO */
1354
1355 if (!spi_is_ready_dt(&config->bus)) {
1356 LOG_ERR("%s: SPI device is not ready", dev->name);
1357 return -ENODEV;
1358 }
1359
1360 if (config->gpio_reset.port != NULL) {
1361 result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
1362 if (result != 0) {
1363 LOG_ERR("%s: failed to initialize GPIO for reset", dev->name);
1364 return result;
1365 }
1366 }
1367
1368 if (config->gpio_start_sync.port != NULL) {
1369 result = gpio_pin_configure_dt(&config->gpio_start_sync, GPIO_OUTPUT_INACTIVE);
1370 if (result != 0) {
1371 LOG_ERR("%s: failed to initialize GPIO for start/sync", dev->name);
1372 return result;
1373 }
1374 }
1375
1376 result = gpio_pin_configure_dt(&config->gpio_data_ready, GPIO_INPUT);
1377 if (result != 0) {
1378 LOG_ERR("%s: failed to initialize GPIO for data ready", dev->name);
1379 return result;
1380 }
1381
1382 result = gpio_pin_interrupt_configure_dt(&config->gpio_data_ready, GPIO_INT_EDGE_TO_ACTIVE);
1383 if (result != 0) {
1384 LOG_ERR("%s: failed to configure data ready interrupt", dev->name);
1385 return -EIO;
1386 }
1387
1388 gpio_init_callback(&data->callback_data_ready, ads114s0x_data_ready_handler,
1389 BIT(config->gpio_data_ready.pin));
1390 result = gpio_add_callback(config->gpio_data_ready.port, &data->callback_data_ready);
1391 if (result != 0) {
1392 LOG_ERR("%s: failed to add data ready callback", dev->name);
1393 return -EIO;
1394 }
1395
1396 #if CONFIG_ADC_ASYNC
1397 k_tid_t tid = k_thread_create(&data->thread, config->stack,
1398 CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE,
1399 ads114s0x_acquisition_thread, (void *)dev, NULL, NULL,
1400 CONFIG_ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT);
1401 k_thread_name_set(tid, "adc_ads114s0x");
1402 #endif
1403
1404 k_busy_wait(ADS114S0X_POWER_ON_RESET_TIME_IN_US);
1405
1406 if (config->gpio_reset.port == NULL) {
1407 result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_RESET);
1408 if (result != 0) {
1409 LOG_ERR("%s: unable to send RESET command", dev->name);
1410 return result;
1411 }
1412 } else {
1413 k_busy_wait(ADS114S0X_RESET_LOW_TIME_IN_US);
1414 gpio_pin_set_dt(&config->gpio_reset, 0);
1415 }
1416
1417 k_busy_wait(ADS114S0X_RESET_DELAY_TIME_IN_US);
1418
1419 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_STATUS, &status);
1420 if (result != 0) {
1421 LOG_ERR("%s: unable to read status register", dev->name);
1422 return result;
1423 }
1424
1425 if (ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) {
1426 LOG_ERR("%s: ADS114 is not yet ready", dev->name);
1427 return -EBUSY;
1428 }
1429
1430 /*
1431 * Activate internal voltage reference during initialization to
1432 * avoid the necessary setup time for it to settle later on.
1433 */
1434 ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
1435
1436 result = ads114s0x_write_register(dev, ADS114S0X_REGISTER_REF, reference_control);
1437 if (result != 0) {
1438 LOG_ERR("%s: unable to set default reference control values", dev->name);
1439 return result;
1440 }
1441
1442 /*
1443 * Ensure that the internal voltage reference is active.
1444 */
1445 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_REF, &reference_control_read);
1446 if (result != 0) {
1447 LOG_ERR("%s: unable to read reference control values", dev->name);
1448 return result;
1449 }
1450
1451 if (reference_control != reference_control_read) {
1452 LOG_ERR("%s: reference control register is incorrect: 0x%02X", dev->name,
1453 reference_control_read);
1454 return -EIO;
1455 }
1456
1457 #ifdef CONFIG_ADC_ADS114S0X_GPIO
1458 data->gpio_enabled = 0x00;
1459 data->gpio_direction = 0x0F;
1460 data->gpio_value = 0x00;
1461
1462 result = ads114s0x_gpio_write_config(dev);
1463
1464 if (result != 0) {
1465 LOG_ERR("%s: unable to configure defaults for GPIOs", dev->name);
1466 return result;
1467 }
1468 #endif
1469
1470 adc_context_unlock_unconditionally(&data->ctx);
1471
1472 return result;
1473 }
1474
1475 static const struct adc_driver_api api = {
1476 .channel_setup = ads114s0x_channel_setup,
1477 .read = ads114s0x_read,
1478 .ref_internal = ADS114S0X_REF_INTERNAL,
1479 #ifdef CONFIG_ADC_ASYNC
1480 .read_async = ads114s0x_adc_read_async,
1481 #endif
1482 };
1483
1484 BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
1485 "CONFIG_ADC_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
1486
1487 #define DT_DRV_COMPAT ti_ads114s08
1488
1489 #define ADC_ADS114S0X_INST_DEFINE(n) \
1490 IF_ENABLED( \
1491 CONFIG_ADC_ASYNC, \
1492 (static K_KERNEL_STACK_DEFINE( \
1493 thread_stack_##n, CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE);)) \
1494 static const struct ads114s0x_config config_##n = { \
1495 .bus = SPI_DT_SPEC_INST_GET( \
1496 n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
1497 IF_ENABLED(CONFIG_ADC_ASYNC, (.stack = thread_stack_##n,)) \
1498 .gpio_reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
1499 .gpio_data_ready = GPIO_DT_SPEC_INST_GET(n, drdy_gpios), \
1500 .gpio_start_sync = GPIO_DT_SPEC_INST_GET_OR(n, start_sync_gpios, {0}), \
1501 .idac_current = DT_INST_PROP(n, idac_current), \
1502 .vbias_level = DT_INST_PROP(n, vbias_level), \
1503 }; \
1504 static struct ads114s0x_data data_##n; \
1505 DEVICE_DT_INST_DEFINE(n, ads114s0x_init, NULL, &data_##n, &config_##n, POST_KERNEL, \
1506 CONFIG_ADC_INIT_PRIORITY, &api);
1507
1508 DT_INST_FOREACH_STATUS_OKAY(ADC_ADS114S0X_INST_DEFINE);
1509
