1/*
2 * Copyright 2021 The Chromium OS Authors
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/g0/stm32g071Xb.dtsi>
9#include <st/g0/stm32g071r(6-8-b)tx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/sensor/ina230.h>
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12
13/ {
14	model = "STM32G071B DEMO board";
15	compatible = "st,stm32g071-demo";
16
17	chosen {
18		zephyr,console = &usart3;
19		zephyr,shell-uart = &usart3;
20		zephyr,sram = &sram0;
21		zephyr,flash = &flash0;
22	};
23
24	leds {
25		compatible = "gpio-leds";
26		red_led_4: led4 {
27			gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
28			label = "TO_REC";
29		};
30		red_led_5: led5 {
31			gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
32			label = "TO_PLUG";
33		};
34		green_led_6: led6 {
35			gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
36			label = "SINK_SPY";
37		};
38		green_led_7: led7 {
39			gpios = <&gpioc 12 GPIO_ACTIVE_HIGH>;
40			label = "SOURCE";
41		};
42	};
43
44	gpio_keys {
45		compatible = "gpio-keys";
46		joy_sel: button0 {
47			label = "JOY_SEL";
48			gpios = <&gpioc 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
49			zephyr,code = <INPUT_KEY_ENTER>;
50		};
51		joy_left: button1 {
52			label = "JOY_LEFT";
53			gpios = <&gpioc 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
54			zephyr,code = <INPUT_KEY_LEFT>;
55		};
56		joy_down: button2 {
57			label = "JOY_DOWN";
58			gpios = <&gpioc 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
59			zephyr,code = <INPUT_KEY_DOWN>;
60		};
61		joy_right: button3 {
62			label = "JOY_RIGHT";
63			gpios = <&gpioc 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
64			zephyr,code = <INPUT_KEY_RIGHT>;
65		};
66		joy_up: button4 {
67			label = "JOY_UP";
68			gpios = <&gpioc 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
69			zephyr,code = <INPUT_KEY_UP>;
70		};
71	};
72
73	cc_config {
74		compatible = "gpio-leds";
75		encc1 {
76			gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
77			label = "ENCC1";
78		};
79
80		encc2 {
81			gpios = <&gpiob 11 GPIO_ACTIVE_HIGH>;
82			label = "ENCC2";
83		};
84
85		rdcc1 {
86			gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
87			label = "RDCC1";
88		};
89	};
90
91	aliases {
92		led0 = &red_led_4;
93		led1 = &red_led_5;
94		led2 = &green_led_6;
95		led3 = &green_led_7;
96		sw0 = &joy_sel;
97		sw1 = &joy_left;
98		sw2 = &joy_down;
99		sw3 = &joy_right;
100		sw4 = &joy_up;
101		watchdog0 = &iwdg;
102	};
103};
104
105&clk_hsi {
106	status = "okay";
107};
108
109&pll {
110	div-m = <1>;
111	mul-n = <8>;
112	div-p = <2>;
113	div-q = <2>;
114	div-r = <2>;
115	clocks = <&clk_hsi>;
116	status = "okay";
117};
118
119&rcc {
120	clocks = <&pll>;
121	clock-frequency = <DT_FREQ_M(64)>;
122	ahb-prescaler = <1>;
123	apb1-prescaler = <1>;
124};
125
126&usart3 {
127	pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
128	pinctrl-names = "default";
129	current-speed = <115200>;
130	status = "okay";
131};
132
133&i2c1 {
134	status = "okay";
135	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
136	pinctrl-names = "default";
137	status = "okay";
138	clock-frequency = <I2C_BITRATE_FAST>;
139
140	/*
141	 * Use U10, INA230 to measure VBUS. I2C Address: 0x40
142	 */
143	vbus_meas: ina230@40 {
144		status = "okay";
145		compatible = "ti,ina230";
146		reg = <0x40>;
147		adc-mode = "Bus voltage continuous";
148		vbus-conversion-time-us = <1100>;
149		vshunt-conversion-time-us = <1100>;
150		avg-count = <1>;
151		current-lsb-microamps = <1000>;
152		rshunt-micro-ohms = <15000>;
153	};
154};
155
156&ucpd1 {
157	status = "okay";
158
159	/*
160	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
161	 * a prescaler who's output feeds the 'half-bit' divider which is used
162	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
163	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
164	 * range is 9 <--> 18 MHz.
165	 *
166	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
167	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
168	 *          +-------+          +-------+   |            +-----------+
169	 *                                         |            +-----------+
170	 *                                         +----------->| ifrgap_cnt|
171	 *                                                      +-----------+
172	 * Requirements:
173	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
174	 *   2. tTransitionWindow - 12 to 20 uSec
175	 *   3. tInterframGap - uSec
176	 *
177	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
178	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
179	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
180	 */
181	psc-ucpdclk = <1>;
182	hbitclkdiv = <27>;
183	pinctrl-0 = <&ucpd1_cc1_pa8 &ucpd1_cc2_pb15>;
184	pinctrl-names = "default";
185};
186
187&iwdg {
188	status = "okay";
189};
190