1.. _nucleo_u5a5zj_q_board: 2 3ST Nucleo U5A5ZJ Q 4################## 5 6Overview 7******** 8 9The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU, 10provides an affordable and flexible way for users to try out new concepts and 11build prototypes by choosing from the various combinations of performance and 12power consumption features. Here are some highlights of the Nucleo U5A5ZJ Q 13board: 14 15 16- STM32U5A5ZJ microcontroller in LQFP144 package 17- Internal SMPS to generate V core logic supply 18- Two types of extension resources: 19 20 - Arduino Uno V3 connectivity 21 - ST morpho extension pin headers for full access to all STM32 I/Os 22 23- On-board ST-LINK/V3E debugger/programmer 24- Flexible board power supply: 25 26 - USB VBUS or external source(3.3V, 5V, 7 - 12V) 27 - ST-Link V3E 28 29- Three users LEDs 30- Two push-buttons: USER and RESET 31- USB Type-C ™ Sink device FS 32 33Hardware 34******** 35 36The STM32U5A5xx devices are an ultra-low-power microcontrollers family (STM32U5 37Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. 38They operate at a frequency of up to 160 MHz. 39 40- Includes ST state-of-the-art patented technology 41- Ultra-low-power with FlexPowerControl: 42 43 - 1.71 V to 3.6 V power supply 44 - -40 °C to +85/125 °C temperature range 45 - Low-power background autonomous mode (LPBAM): autonomous peripherals with 46 DMA, functional down to Stop 2 mode 47 - VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM 48 - 150 nA Shutdown mode (24 wake-up pins) 49 - 195 nA Standby mode (24 wake-up pins) 50 - 480 nA Standby mode with RTC 51 - 2 µA Stop 3 mode with 40-Kbyte SRAM 52 - 8.2 µA Stop 3 mode with 2.5-Mbyte SRAM 53 - 4.65 µA Stop 2 mode with 40-Kbyte SRAM 54 - 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM 55 - 18.5 µA/MHz Run mode at 3.3 V 56 57- Core: 58 59 - Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, 60 and FPU ART Accelerator 61 - 32-Kbyte ICACHE allowing 0-wait-state execution from flash and external 62 memories: frequency up to 160 MHz, 240 DMIPS 63 - 16-Kbyte DCACHE1 for external memories 64 65- Power management: 66 67 - Embedded regulator (LDO) and SMPSstep-down converter supporting switch 68 on-the-fly and voltage scaling 69 70- Benchmarks: 71 72 - 1.5 DMIPS/MHz (Drystone 2.1) 73 - 655 CoreMark® (4.09 CoreMark®/MHz) 74 - 369 ULPMark™-CP 75 - 89 ULPMark™-PP 76 - 47.2 ULPMark™-CM 77 - 120000 SecureMark™-TLS 78 79- Memories: 80 81 - 4-Mbyte flash memory with ECC, 2 banks readwhile-write, including 512 Kbytes 82 with 100 kcycles 83 - With SRAM3 ECC off: 2514-Kbyte RAM including 66 Kbytes with ECC 84 - With SRAM3 ECC on: 2450-Kbyte RAMincluding 322 Kbytes with ECC 85 - External memory interface supporting SRAM,PSRAM, NOR, NAND, and FRAM memories 86 - 2 Octo-SPI memory interfaces 87 - 16-bit HSPI memory interface up to 160 MHz 88 89- Rich graphic features: 90 91 - Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and 92 perspective correct texture mapping 93 - 16-Kbyte DCACHE2 94 - Chrom-ART Accelerator (DMA2D) for smoothmotion and transparency effects 95 - Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization 96 - MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each 97 - LCD-TFT controller (LTDC) 98 - Digital camera interface 99 100- General-purpose input/outputs: 101 102 - Up to 156 fast I/Os with interrupt capability most 5V-tolerant and 103 up to 14 I/Os with independent supply down to 1.08 V 104 105- Clock management: 106 107 - 4 to 50 MHz crystal oscillator 108 - 32 kHz crystal oscillator for RTC (LSE) 109 - Internal 16 MHz factory-trimmed RC (± 1 %) 110 - Internal low-power 32 kHz RC (± 5 %) 111 - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one 112 autotrimmed by LSE (better than ± 0.25 % accuracy) 113 - Internal 48 MHz 114 - 5 PLLs for system clock, USB, audio, ADC, DSI 115 116- Security and cryptography: 117 118 - SESIP3 and PSA Level 3 Certified Assurance Target 119 - Arm® TrustZone® and securable I/Os, memories, and peripherals 120 - Flexible life cycle scheme with RDP andpassword-protected debug 121 - Root of trust thanks to unique boot entry and secure hide-protection area (HDP) 122 - Secure firmware installation (SFI) thanks to embedded root secure services (RSS) 123 - Secure data storage with hardware unique key (HUK) 124 - Secure firmware upgrade support with TF-M 125 - 2 AES coprocessors including one with DPA resistance 126 - Public key accelerator, DPA resistant 127 - On-the-fly decryption of Octo-SPI external memories 128 - HASH hardware accelerator 129 - True random number generator, NIST SP800-90B compliant 130 - 96-bit unique ID 131 - 512-byte OTP (one-time programmable) 132 - Active tampers 133 134- Up to 17 timers, 2 watchdogs and RTC: 135 136 - 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general 137 purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), 138 2 SysTick timers, and 2 watchdogs 139 - RTC with hardware calendar, alarms, and calibration 140 141- Up to 25 communication peripherals: 142 143 - 1 USB Type-C®/USB power delivery controller 144 - 1 USB OTG high-speed with embedded PHY 145 - 2 SAIs (serial audio interface) 146 - 6 I2C FM+(1 Mbit/s), SMBus/PMBus™ 147 - 7 USARTs (ISO 7816, LIN, IrDA, modem) 148 - 3 SPIs (6x SPIs with OCTOSPI/HSPI) 149 - 1 CAN FD controller 150 - 2 SDMMC interfaces 151 - 1 multifunction digital filter (6 filters) + 1 audio digital filter 152 with sound-activity detection 153 - Parallel synchronous slave interface 154 155- Mathematical coprocessor: 156 157 - CORDIC for trigonometric functions acceleration 158 - FMAC (filter mathematical accelerator) 159 160- Rich analog peripherals (independent supply): 161 162 - 2 14-bit ADC 2.5-Msps with hardware oversampling 163 - 1 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode 164 - 12-bit DAC (2 channels), low-power sample, and hold, autonomous in Stop 2 mode 165 - 2 operational amplifiers with built-in PGA 166 - 2 ultra-low-power comparators 167 168- ECOPACK2 compliant packages 169 170More information about STM32U5A5ZJ can be found here: 171 172- `STM32U5A5ZJ on www.st.com`_ 173- `STM32U5A5 reference manual`_ 174 175Supported Features 176================== 177 178The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features: 179 180+-----------+------------+-------------------------------------+ 181| Interface | Controller | Driver/Component | 182+===========+============+=====================================+ 183| CAN/CANFD | on-chip | canbus | 184+-----------+------------+-------------------------------------+ 185| CLOCK | on-chip | reset and clock control | 186+-----------+------------+-------------------------------------+ 187| DAC | on-chip | DAC Controller | 188+-----------+------------+-------------------------------------+ 189| GPIO | on-chip | gpio | 190+-----------+------------+-------------------------------------+ 191| I2C | on-chip | i2c | 192+-----------+------------+-------------------------------------+ 193| NVIC | on-chip | nested vector interrupt controller | 194+-----------+------------+-------------------------------------+ 195| PINMUX | on-chip | pinmux | 196+-----------+------------+-------------------------------------+ 197| SPI | on-chip | spi | 198+-----------+------------+-------------------------------------+ 199| UART | on-chip | serial port-polling; | 200| | | serial port-interrupt | 201+-----------+------------+-------------------------------------+ 202| WATCHDOG | on-chip | independent watchdog | 203+-----------+------------+-------------------------------------+ 204| BKP SRAM | on-chip | Backup SRAM | 205+-----------+------------+-------------------------------------+ 206| RNG | on-chip | True Random number generator | 207+-----------+------------+-------------------------------------+ 208| RTC | on-chip | rtc | 209+-----------+------------+-------------------------------------+ 210 211 212Other hardware features are not yet supported on this Zephyr port. 213 214The default configuration can be found in the defconfig file: 215:zephyr_file:`boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig` 216 217 218Connections and IOs 219=================== 220 221Nucleo U5A5ZJ Q Board has 10 GPIO controllers. These controllers are responsible 222for pin muxing, input/output, pull-up, etc. 223 224For more details please refer to `STM32 Nucleo-144 board User Manual`_. 225 226Default Zephyr Peripheral Mapping: 227---------------------------------- 228 229 230- CAN/CANFD_TX: PD1 231- CAN/CANFD_RX: PD0 232- DAC1_OUT1 : PA4 233- I2C_1_SCL : PB8 234- I2C_1_SDA : PB9 235- I2C_2_SCL : PF1 236- I2C_2_SDA : PF0 237- LD1 : PC7 238- LD2 : PB7 239- LD3 : PG2 240- LPUART_1_TX : PG7 241- LPUART_1_RX : PG8 242- SPI_1_NSS : PA4 243- SPI_1_SCK : PA5 244- SPI_1_MISO : PA6 245- SPI_1_MOSI : PA7 246- UART_1_TX : PA9 247- UART_1_RX : PA10 248- UART_2_TX : PD5 249- UART_2_RX : PD6 250- USER_PB : PC13 251 252System Clock 253------------ 254 255Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, 256as well as main PLL clock. By default System clock is driven by PLL clock at 257160MHz, driven by 4MHz medium speed internal oscillator. 258 259Serial Port 260----------- 261 262Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to 263USART1. Default settings are 115200 8N1. 264 265 266Backup SRAM 267----------- 268 269In order to test backup SRAM you may want to disconnect VBAT from VDD. You can 270do it by removing ``SB50`` jumper on the back side of the board. 271 272 273Programming and Debugging 274************************* 275 276Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface. 277This probe allows to flash the board using various tools. 278 279Flashing 280======== 281 282Board is configured to be flashed using west STM32CubeProgrammer runner. 283Installation of `STM32CubeProgrammer`_ is then required to flash the board. 284 285Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be 286used to flash and debug the board if west is told to use it as runner, 287which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. 288 289For pyocd additional target information needs to be installed. 290This can be done by executing the following commands. 291 292.. code-block:: console 293 294 $ pyocd pack --update 295 $ pyocd pack --install stm32u5 296 297 298Flashing an application to Nucleo U5A5ZJ Q 299------------------------------------------ 300 301Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. 302Then build and flash an application. Here is an example for the 303:ref:`hello_world` application. 304 305Run a serial host program to connect with your Nucleo board: 306 307.. code-block:: console 308 309 $ minicom -D /dev/ttyACM0 310 311Then build and flash the application. 312 313.. zephyr-app-commands:: 314 :zephyr-app: samples/hello_world 315 :board: nucleo_u5a5zj_q 316 :goals: build flash 317 318You should see the following message on the console: 319 320.. code-block:: console 321 322 Hello World! arm 323 324Debugging 325========= 326 327Default flasher for this board is openocd. It could be used in the usual way. 328Here is an example for the :zephyr:code-sample:`blinky` application. 329 330.. zephyr-app-commands:: 331 :zephyr-app: samples/basic/blinky 332 :board: nucleo_u5a5zj_q 333 :goals: debug 334 335Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts 336(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` 337(which is used for initialization) is available in the PATH. 338 339.. _STM32 Nucleo-144 board User Manual: 340 https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf 341 342.. _STM32U5A5ZJ on www.st.com: 343 https://www.st.com/en/microcontrollers/stm32u5a5zj.html 344 345.. _STM32U5A5 reference manual: 346 https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf 347 348.. _STM32CubeProgrammer: 349 https://www.st.com/en/development-tools/stm32cubeprog.html 350 351.. _STMicroelectronics customized version of OpenOCD: 352 https://github.com/STMicroelectronics/OpenOCD 353
