1.. _nucleo_h533re_board: 2 3ST Nucleo H533RE 4################ 5 6Overview 7******** 8 9The Nucleo H533RE board is designed as an affordable development platform for 10STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H533RET6 11microcontroller with TrustZone |reg|. 12Here are some highlights of the Nucleo H533RE board: 13 14- STM32H533RE microcontroller featuring 512 kbytes of Flash memory and 272 Kbytes of 15 SRAM in LQFP64 package 16 17- Board connectors: 18 19 - USB Type-C |trade| Sink device FS 20 - ST Zio expansion connector including Arduino Uno V3 connectivity (CN5, CN6, CN8, CN9) 21 - ST morpho extension connector (CN7, CN10) 22 23- Flexible board power supply: 24 25 - 5V_USB_STLK from ST-Link USB connector 26 - VIN (7 - 12V, 0.8) supplied via pin header CN6 pin 8 or CN7 pin 24 27 - ESV on the ST morpho connector CN7 Pin 6 (5V, O.5A) 28 - VBUS_STLK from a USB charger via the ST-LINK USB connector 29 - VBUSC from the USB user connector (5V, 0.5A) 30 - 3V3_EXT supplied via a pin header CN6 pin 4 or CN7 pin 16 (3.3V, 1.3A) 31 32- On-board ST-LINK/V3EC debugger/programmer 33 34 - mass storage 35 - Virtual COM port 36 - debug port 37 38- One user LED shared with ARDUINO |reg| Uno V3 39- Two push-buttons: USER and RESET 40- 32.768 kHz crystal oscillator 41 42More information about the board can be found at the `NUCLEO_H533RE website`_. 43 44.. image:: img/nucleo_h533re.jpg 45 :align: center 46 :alt: NUCLEO H533RE 47 48Hardware 49******** 50 51The STM32H533xx devices are high-performance microcontrollers from the STM32H5 52Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. 53They operate at a frequency of up to 250 MHz. 54 55- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. 56- Performance benchmark: 57 58 - 375 DMPIS/MHz (Dhrystone 2.1) 59 60- Security 61 62 - Arm |reg| TrustZone |reg| with Armv8-M mainline security extension 63 - Up to eight configurable SAU regions 64 - TrustZone |reg| aware and securable peripherals 65 - Flexible life cycle scheme with secure debug authentication 66 - SESIP3 and PSA Level 3 certified assurance target 67 - Preconfigured immutable root of trust (ST-iROT) 68 - SFI (secure firmware installation) 69 - Root of trust thanks to unique boot entry and secure hide protection area (HDP) 70 - Secure data storage with hardware unique key (HUK) 71 - Secure firmware upgrade support with TF-M 72 - Two AES coprocessors including one with DPA resistance 73 - Public key accelerator, DPA resistant 74 - On-the-fly decryption of Octo-SPI external memories 75 - HASH hardware accelerator 76 - True random number generator, NIST SP800-90B compliant 77 - 96-bit unique ID 78 - Active tampers 79 80- Clock management: 81 82 - 24 MHz crystal oscillator (HSE) 83 - 32 kHz crystal oscillator for RTC (LSE) 84 - Internal 64 MHz (HSI) trimmable by software 85 - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) 86 - Internal 4 MHz oscillator (CSI), trimmable by software 87 - Internal 48 MHz (HSI48) with recovery system 88 - 3 PLLs for system clock, USB, audio, ADC 89 90- Power management 91 92 - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry 93 - Embedded SMPS step-down converter 94 95- RTC with HW calendar, alarms and calibration 96- Up to 112 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V 97- Up to 16 timers and 2 watchdogs 98 99 - 8x 16-bit 100 - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 101 - 2x 16-bit low-power 16-bit timers (available in Stop mode) 102 - 2x watchdogs 103 - 2x SysTick timer 104 105- Memories 106 107 - Up to 512 Kbytes Flash, 2 banks read-while-write 108 - 1 Kbyte OTP (one-time programmable) 109 - 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC) 110 - 2 Kbytes of backup SRAM available in the lowest power modes 111 - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories 112 - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats 113 - 1x SD/SDIO/MMC interfaces 114 115- Rich analog peripherals (independent supply) 116 117 - 2x 12-bit ADC with up to 5 MSPS in 12-bit 118 - 1x 12-bit DAC with 2 channels 119 - 1x Digital temperature sensor 120 - Voltage reference buffer 121 122- 34x communication interfaces 123 124 - 1x USB Type-C / USB power-delivery controller 125 - 1x USB 2.0 full-speed host and device (crystal-less) 126 - 3x I2C FM+ interfaces (SMBus/PMBus) 127 - 2x I3C interface 128 - 6x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) 129 - 1x LP UART 130 - 4x SPIs including 3 muxed with full-duplex I2S 131 - 4x additional SPI from 4x USART when configured in Synchronous mode 132 - 2x FDCAN 133 - 1x SDMMC interface 134 - 2x 16 channel DMA controllers 135 - 1x 8- to 14- bit camera interface 136 - 1x HDMI-CEC 137 - 1x 16-bit parallel slave synchronous-interface 138 139- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| 140 141More information about STM32H533RE can be found here: 142 143- `STM32H533re on www.st.com`_ 144- `STM32H533 reference manual`_ 145 146Supported Features 147================== 148 149The Zephyr nucleo_h533re board configuration supports the following hardware features: 150 151+-----------+------------+-------------------------------------+ 152| Interface | Controller | Driver/Component | 153+===========+============+=====================================+ 154| CLOCK | on-chip | reset and clock control | 155+-----------+------------+-------------------------------------+ 156| GPIO | on-chip | gpio | 157+-----------+------------+-------------------------------------+ 158| NVIC | on-chip | nested vector interrupt controller | 159+-----------+------------+-------------------------------------+ 160| PINMUX | on-chip | pinmux | 161+-----------+------------+-------------------------------------+ 162| PWM | on-chip | PWM | 163+-----------+------------+-------------------------------------+ 164| RNG | on-chip | True Random number generator | 165+-----------+------------+-------------------------------------+ 166| RTC | on-chip | Real Time Clock | 167+-----------+------------+-------------------------------------+ 168| UART | on-chip | serial port-polling; | 169| | | serial port-interrupt | 170+-----------+------------+-------------------------------------+ 171| WATCHDOG | on-chip | independent watchdog | 172+-----------+------------+-------------------------------------+ 173| ADC | on-chip | ADC Controller | 174+-----------+------------+-------------------------------------+ 175 176Other hardware features are not yet supported on this Zephyr port. 177 178The default configuration can be found in the defconfig and dts files: 179 180- Secure target: 181 182 - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re_defconfig` 183 - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re.dts` 184 185Zephyr board options 186==================== 187 188The STM32H533 is a SoC with Cortex-M33 architecture. Zephyr provides support 189for building for Secure firmware. 190 191The BOARD options are summarized below: 192 193+----------------------+-----------------------------------------------+ 194| BOARD | Description | 195+======================+===============================================+ 196| nucleo_h533re | For building Secure firmware | 197+----------------------+-----------------------------------------------+ 198 199Connections and IOs 200=================== 201 202Nucleo H533RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, 203input/output, pull-up, etc. 204 205For more details please refer to `STM32H5 Nucleo-64 board User Manual`_. 206 207Default Zephyr Peripheral Mapping: 208---------------------------------- 209 210- ADC1 channel 0 input: PA0 211- USART1 TX/RX : PB14/PB15 (Arduino USART1) 212- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PA4 213- UART2 TX/RX : PA2/PA3 (VCP) 214- USER_PB : PC13 215 216System Clock 217------------ 218 219Nucleo H533RE System Clock could be driven by internal or external oscillator, 220as well as main PLL clock. By default System clock is driven by PLL clock at 221240MHz, driven by an 24MHz high-speed external clock. 222 223Serial Port 224----------- 225 226Nucleo H533RE board has up to 4 USARTs, 2 UARTs, and one LPUART. The Zephyr console output is assigned 227to USART2. Default settings are 115200 8N1. 228 229Programming and Debugging 230************************* 231 232Applications for the ``nucleo_h533re`` board can be built and 233flashed in the usual way (see :ref:`build_an_application` and 234:ref:`application_run` for more details). 235 236OpenOCD Support 237=============== 238 239For now, openocd support for stm32h5 is not available on upstream OpenOCD. 240You can check `OpenOCD official Github mirror`_. 241In order to use it though, you should clone from the cutomized 242`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines. 243Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in 244:zephyr_file:`boards/st/nucleo_h533re/board.cmake` to point the build 245to the paths of the OpenOCD binary and its scripts, before 246including the common openocd.board.cmake file: 247 248 .. code-block:: none 249 250 set(OPENOCD "<path_to_openocd_repo>/src/openocd" CACHE FILEPATH "" FORCE) 251 set(OPENOCD_DEFAULT_PATH <path_to_opneocd_repo>/tcl) 252 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) 253 254Flashing 255======== 256 257Nucleo H533RE board includes an ST-LINK/V3EC embedded debug tool interface. 258This probe allows to flash the board using various tools. 259 260Board is configured to be flashed using west STM32CubeProgrammer runner. 261Installation of `STM32CubeProgrammer`_ is then required to flash the board. 262 263Alternatively, pyocd or jlink via an external probe can also be used to flash 264and debug the board if west is told to use it as runner, which can be done by 265passing either or ``-r pyocd``, or ``-r jlink``. 266 267For pyocd additional target information needs to be installed. 268This can be done by executing the following commands. 269 270.. code-block:: console 271 272 $ pyocd pack --update 273 $ pyocd pack --install stm32h5 274 275 276Alternatively, the openocd interface will be supported by a next openocd version. 277When available, OpenOCD could be used in the same way as other tools. 278 279 280Flashing an application to Nucleo H533RE 281------------------------------------------ 282 283Connect the Nucleo H533RE to your host computer using the USB port. 284Then build and flash an application. Here is an example for the 285:ref:`hello_world` application. 286 287Run a serial host program to connect with your Nucleo board: 288 289.. code-block:: console 290 291 $ minicom -D /dev/ttyACM0 292 293Then build and flash the application. 294 295.. zephyr-app-commands:: 296 :zephyr-app: samples/hello_world 297 :board: nucleo_h533re 298 :goals: build flash 299 300You should see the following message on the console: 301 302.. code-block:: console 303 304 Hello World! nucleo_h533re 305 306Debugging 307========= 308 309You can debug an application in the usual way. Here is an example for the 310:zephyr:code-sample:`blinky` application. 311 312.. zephyr-app-commands:: 313 :zephyr-app: samples/basic/blinky 314 :board: nucleo_h533re 315 :goals: debug 316 317.. _NUCLEO_H533RE website: 318 https://www.st.com/en/evaluation-tools/nucleo-h533re 319 320.. _STM32H5 Nucleo-64 board User Manual: 321 https://www.st.com/resource/en/user_manual/um3121-stm32h5-nucleo64-board-mb1814-stmicroelectronics.pdf 322 323.. _STM32H533RE on www.st.com: 324 https://www.st.com/en/microcontrollers-microprocessors/stm32h533re 325 326.. _STM32H533 reference manual: 327 https://www.st.com/resource/en/reference_manual/rm0481-stm32h533-stm32h563-stm32h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf 328 329.. _STM32CubeProgrammer: 330 https://www.st.com/en/development-tools/stm32cubeprog.html 331 332.. _OpenOCD official Github mirror: 333 https://github.com/openocd-org/openocd/ 334 335.. _STMicroelectronics OpenOCD Github: 336 https://github.com/STMicroelectronics/OpenOCD/tree/openocd-cubeide-r6 337
