1/* 2 * Copyright (c) 2022 Seco Spa 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8#include <st/f3/stm32f302Xc.dtsi> 9#include <st/f3/stm32f302v(b-c)tx-pinctrl.dtsi> 10 11/ { 12 model = "SECO SBC-3.5-PX30 board (STM32F302VCT6)"; 13 compatible = "seco,stm32f3-d23"; 14 15 chosen { 16 zephyr,console = &usart1; 17 zephyr,code-partition = &slot0_partition; 18 zephyr,shell-uart = &usart1; 19 zephyr,sram = &sram0; 20 zephyr,flash = &flash0; 21 zephyr,canbus = &can1; 22 }; 23 24 leds { 25 compatible = "gpio-leds"; 26 led_1: led_1 { 27 gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; 28 label = "LED-1"; 29 }; 30 led_2: led_2 { 31 gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; 32 label = "LED-2"; 33 }; 34 }; 35 36 out_3p3v_pwr: 3p3v-out-pwr-ctrl { 37 compatible = "regulator-fixed"; 38 regulator-name = "3p3v-out-pwr-ctrl"; 39 enable-gpios = <&gpioe 7 GPIO_ACTIVE_HIGH>; 40 regulator-always-on; 41 regulator-boot-on; 42 status = "okay"; 43 }; 44 45 out_gpio_bufa_pwr: out-gpio-bufa-pwr-ctrl { 46 compatible = "regulator-fixed"; 47 regulator-name = "out-gpio-bufa-pwr-ctrl"; 48 enable-gpios = <&gpiof 2 GPIO_ACTIVE_LOW>; 49 regulator-boot-on; 50 status = "okay"; 51 }; 52 53 out_gpio_bufb_pwr: out-gpio-bufb-pwr-ctrl { 54 compatible = "regulator-fixed"; 55 regulator-name = "out-gpio-bufb-pwr-ctrl"; 56 enable-gpios = <&gpiof 4 GPIO_ACTIVE_LOW>; 57 regulator-boot-on; 58 status = "okay"; 59 }; 60 61 in_gpio_buf_pwr: in-gpio-buf-pwr-ctrl { 62 compatible = "regulator-fixed"; 63 regulator-name = "in-gpio-buf-pwr-ctrl"; 64 enable-gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; 65 regulator-boot-on; 66 status = "okay"; 67 }; 68 69 transceiver0: can-phy0 { 70 compatible = "nxp,tja1040", "can-transceiver-gpio"; 71 standby-gpios = <&gpiod 0 GPIO_ACTIVE_HIGH>; 72 max-bitrate = <1000000>; 73 #phy-cells = <0>; 74 }; 75 76 aliases { 77 led0 = &led_1; 78 led1 = &led_2; 79 }; 80}; 81 82&clk_lsi { 83 status = "okay"; 84}; 85 86&clk_hse { 87 clock-frequency = <DT_FREQ_M(8)>; 88 status = "okay"; 89}; 90 91&pll { 92 prediv = <1>; 93 mul = <9>; 94 clocks = <&clk_hse>; 95 status = "okay"; 96}; 97 98&rcc { 99 clocks = <&pll>; 100 clock-frequency = <DT_FREQ_M(72)>; 101 ahb-prescaler = <1>; 102 apb1-prescaler = <2>; 103 apb2-prescaler = <1>; 104 status = "okay"; 105}; 106 107/* Debug Serial */ 108&usart1 { 109 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; 110 pinctrl-names = "default"; 111 current-speed = <115200>; 112 status = "okay"; 113}; 114 115/* Modbus */ 116&usart2 { 117 pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6 118 &usart2_cts_pd3 &usart2_rts_pd4>; 119 pinctrl-names = "default"; 120 current-speed = <115200>; 121}; 122 123/* RS-485 */ 124&usart3 { 125 pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11 126 &usart3_rts_pd12>; 127 pinctrl-names = "default"; 128 current-speed = <115200>; 129}; 130 131&uart5 { 132 pinctrl-0 = <&uart5_tx_pc12 &uart5_rx_pd2>; 133 pinctrl-names = "default"; 134 current-speed = <115200>; 135}; 136 137&i2c1 { 138 pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; 139 pinctrl-names = "default"; 140 clock-frequency = <I2C_BITRATE_FAST>; 141 status = "okay"; 142}; 143 144&i2c2 { 145 /* alternate config usart1 */ 146 pinctrl-0 = <&i2c2_scl_pa9 &i2c2_sda_pa10>; 147 pinctrl-names = "default"; 148 clock-frequency = <I2C_BITRATE_FAST>; 149}; 150 151&spi1 { 152 pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pb3 153 &spi1_miso_pb4 &spi1_mosi_pb5>; 154 pinctrl-names = "default"; 155 status = "okay"; 156}; 157 158&spi2 { 159 pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13 160 &spi2_miso_pb14 &spi2_mosi_pb15>; 161 pinctrl-names = "default"; 162 status = "okay"; 163}; 164 165zephyr_udc0: &usb { 166 pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; 167 pinctrl-names = "default"; 168 status = "okay"; 169}; 170 171&rtc { 172 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, 173 <&rcc STM32_SRC_LSI RTC_SEL(2)>; 174 status = "okay"; 175}; 176 177&can1 { 178 pinctrl-0 = <&can_rx_pb8 &can_tx_pb9>; 179 pinctrl-names = "default"; 180 phys = <&transceiver0>; 181 status = "okay"; 182}; 183 184&flash0 { 185 partitions { 186 compatible = "fixed-partitions"; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 boot_partition: partition@0 { 190 label = "mcuboot"; 191 reg = <0x00000000 0x00010000>; 192 read-only; 193 }; 194 /* 195 * The flash starting at 0x00010000 and ending at 196 * 0x0001ffff (sectors 16-31) is reserved for use 197 * by the application. 198 */ 199 slot0_partition: partition@20000 { 200 label = "image-0"; 201 reg = <0x00020000 0x00008000>; 202 }; 203 slot1_partition: partition@28000 { 204 label = "image-1"; 205 reg = <0x00028000 0x00008000>; 206 }; 207 storage_partition: partition@30000 { 208 label = "storage"; 209 reg = <0x00030000 0x00002000>; 210 }; 211 scratch_partition: partition@32000 { 212 label = "image-scratch"; 213 reg = <0x00032000 0x00008000>; 214 }; 215 }; 216}; 217 218&iwdg { 219 status = "okay"; 220}; 221 222&timers1 { 223 st,prescaler = <10000>; 224 status = "okay"; 225 pwm1: pwm { 226 pinctrl-0 = <&tim1_ch1_pe9 &tim1_ch2n_pe10 &tim1_ch2_pe11 227 &tim1_ch3n_pe12 &tim1_ch3_pe13 &tim1_ch4_pe14>; 228 pinctrl-names = "default"; 229 status = "okay"; 230 }; 231}; 232 233&timers4 { 234 st,prescaler = <10000>; 235 status = "okay"; 236 pwm4: pwm { 237 pinctrl-0 = <&tim4_ch2_pd13 &tim4_ch3_pd14 &tim4_ch4_pd15>; 238 pinctrl-names = "default"; 239 status = "okay"; 240 }; 241}; 242
