1/*
2 * NOTE: Autogenerated file by gen_board_pinctrl.py
3 * for MK66FN2M0VMD18/signal_configuration.xml
4 *
5 * Copyright (c) 2022, NXP
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9
10#include <nxp/kinetis/MK66FN2M0VMD18-pinctrl.h>
11
12&pinctrl {
13	mdio_default: mdio_default {
14		group0 {
15			pinmux = <RMII0_MDIO_PTB0>;
16			drive-strength = "low";
17			drive-open-drain;
18			bias-pull-up;
19			slew-rate = "fast";
20		};
21		group1 {
22			pinmux = <RMII0_MDC_PTB1>;
23			drive-strength = "low";
24			slew-rate = "fast";
25		};
26	};
27
28	enet_default: enet_default {
29		group0 {
30			pinmux = <RMII0_RXER_PTA5>,
31				<RMII0_RXD1_PTA12>,
32				<RMII0_RXD0_PTA13>,
33				<RMII0_CRS_DV_PTA14>,
34				<RMII0_TXEN_PTA15>,
35				<RMII0_TXD1_PTA17>,
36				<RMII0_TXD0_PTA16>;
37			drive-strength = "low";
38			slew-rate = "fast";
39		};
40	};
41
42	flexcan0_default: flexcan0_default {
43		group0 {
44			pinmux = <CAN0_RX_PTB19>,
45				<CAN0_TX_PTB18>;
46			drive-strength = "low";
47			slew-rate = "fast";
48		};
49	};
50
51	flexcan1_default: flexcan1_default {
52		group0 {
53			pinmux = <CAN1_RX_PTC16>,
54				<CAN1_TX_PTC17>;
55			drive-strength = "low";
56			slew-rate = "fast";
57		};
58	};
59
60	ftm0_default: ftm0_default {
61		group0 {
62			pinmux = <FTM0_CH0_PTC1>,
63				<FTM0_CH3_PTA6>,
64				<FTM0_CH4_PTD4>,
65				<FTM0_CH5_PTD5>;
66			drive-strength = "low";
67			slew-rate = "fast";
68		};
69	};
70
71	/* conflicts with UART2 */
72	ftm3_default: ftm3_default {
73		group0 {
74			pinmux = <FTM3_CH1_PTD1>,
75				<FTM3_CH4_PTC8>,
76				<FTM3_CH5_PTC9>,
77				<FTM3_CH6_PTE11>,
78				<FTM3_CH7_PTE12>;
79			drive-strength = "low";
80			slew-rate = "fast";
81		};
82	};
83
84	i2c0_default: i2c0_default {
85		group0 {
86			pinmux = <I2C0_SCL_PTE24>;
87			drive-strength = "low";
88			slew-rate = "fast";
89		};
90		group1 {
91			pinmux = <I2C0_SDA_PTE25>;
92			drive-strength = "low";
93			slew-rate = "fast";
94			drive-open-drain;
95		};
96	};
97
98	i2c1_default: i2c1_default {
99		group0 {
100			pinmux = <I2C1_SCL_PTC10>;
101			drive-strength = "low";
102			slew-rate = "fast";
103		};
104		group1 {
105			pinmux = <I2C1_SDA_PTC11>;
106			drive-strength = "low";
107			slew-rate = "fast";
108			drive-open-drain;
109		};
110	};
111
112	lpuart0_default: lpuart0_default {
113		group0 {
114			pinmux = <LPUART0_RX_PTD8>;
115			drive-strength = "low";
116			bias-pull-up;
117			slew-rate = "fast";
118		};
119		group1 {
120			pinmux = <LPUART0_TX_PTD9>;
121			drive-strength = "low";
122			slew-rate = "fast";
123		};
124	};
125
126	spi0_default: spi0_default {
127		group0 {
128			pinmux = <SPI0_PCS2_PTC2>,
129				<SPI0_SCK_PTC5>,
130				<SPI0_SIN_PTC7>,
131				<SPI0_SOUT_PTC6>;
132			drive-strength = "low";
133			slew-rate = "fast";
134		};
135	};
136
137	spi1_default: spi1_default {
138		group0 {
139			pinmux = <SPI1_PCS0_PTB10>,
140				<SPI1_PCS1_PTB9>,
141				<SPI1_SCK_PTB11>,
142				<SPI1_SIN_PTB17>,
143				<SPI1_SOUT_PTB16>;
144			drive-strength = "low";
145			slew-rate = "fast";
146		};
147	};
148
149	spi2_default: spi2_default {
150		group0 {
151			pinmux = <SPI2_PCS0_PTB20>,
152				<SPI2_SCK_PTB21>,
153				<SPI2_SIN_PTB23>,
154				<SPI2_SOUT_PTB22>;
155			drive-strength = "low";
156			slew-rate = "fast";
157		};
158	};
159
160	uart0_default: uart0_default {
161		group0 {
162			pinmux = <UART0_RX_PTA1>,
163				<UART0_TX_PTA2>;
164			drive-strength = "low";
165			slew-rate = "fast";
166		};
167	};
168
169	uart1_default: uart1_default {
170		group0 {
171			pinmux = <UART1_RX_PTC3>,
172				<UART1_TX_PTC4>;
173			drive-strength = "low";
174			slew-rate = "fast";
175		};
176	};
177
178	/* conflicts with FTM3 */
179	uart2_default: uart2_default {
180		group0 {
181			pinmux = <UART2_RX_PTD2>,
182				<UART2_TX_PTD3>;
183			drive-strength = "low";
184			slew-rate = "fast";
185		};
186	};
187
188	uart4_default: uart4_default {
189		group0 {
190			pinmux = <UART4_CTS_b_PTC13>,
191				<UART4_RTS_b_PTE27>,
192				<UART4_RX_PTC14>,
193				<UART4_TX_PTC15>;
194			drive-strength = "low";
195			slew-rate = "fast";
196		};
197	};
198
199};
200